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This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million operations per second (MOPS) per mW at 162 MOPS (32 bits), improving the first-generation Parallel Ultra-Low-Power (PULP) architecture by 6.4 and 3.2 times in performance and energy efficiency, respectively. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., >1012) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO2-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases. [ABSTRACT FROM PUBLISHER]

Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance. [ABSTRACT FROM AUTHOR]

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5 . A novel procedure, named R–SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R–SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R–SET pulse based on a time reference scheme is proposed and discussed. [ABSTRACT FROM PUBLISHER]

Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. [ABSTRACT FROM AUTHOR]

Emerging nonvolatile memories (eNVMs) such as phase-change random access memories (PCRAMs) or oxide-based resistive random access memories (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for field-programmable gate arrays (FPGAs) using eNVMs. We propose an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switcarrangement. We show that these blocks yield an improvement in area and write time of up to 3× and 33×, respectively, versus a regular Flash implementation. By integrating the designed blocks in an FPGA, we demonstrate an area and delay reduction of up to 28% and 34%, respectively, on a set of benchmark circuits. These reductions are due to the eNVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack. [ABSTRACT FROM PUBLISHER]

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed. [ABSTRACT FROM AUTHOR]

With forecasted hundreds of processing elements (PEs), future embedded systems will be able to handle multiple applications with very diverse running constraints. Systems will integrate distributed decision capabilities. In order to control the power and temperature, dynamic voltage frequency scalings (DVFSs) are applied at PE level. At system level, it implies to dynamically manage the different voltage/frequency couples of each tile to obtain a global optimization. This paper introduces a scalable multiobjective approach based on game theory, which adjusts at run-time the frequency of each PE. It aims at reducing the tile temperature while maintaining the synchronization between application tasks. Results show that the proposed run-time algorithm requires an average of 20 calculation cycles to find the solution for a 100-processor platform and reaches equivalent performances when comparing with an offline method. Temperature reductions of about 23% were achieved on a demonstrative test-case. [ABSTRACT FROM AUTHOR]

In order to face the inherent complexity of new radio access technologies and to address the development of multi-standard devices, an innovative reconfigurable baseband architecture based on a distributed control and communication framework is proposed. This architecture is tailored to the possibilities and limitations of next-generation CMOS nanotechnologies in terms of leakage and timing closure. A combination of technology features, message passing control model, network-on-chip, asynchronous implementation, clocking and power reduction policies is used. The 79.5 mm² chip was manufactured in a 130 nm CMOS technology and is integrated in a prototyping platform to perform real-time experimentation of advanced MIMO OFDM based telecom techniques. It is composed of 23 functional units, such as computing intensive IPs, channel coding blocks, programmable DMA engines, an ARM946ES core, and an Ethernet interface. These elements are interconnected via an asynchronous layered Network-on-Chip using an interface that controls the communication and configuration parameters during application scheduling. [ABSTRACT FROM AUTHOR]