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Resistive Random Access Memory (RRAM) is a prominent contender in the realm of emerging non-volatile memory technologies owing to its numerous advantages like simple structure, low power usage, high speed, and exceptional scalability. In the current study, RRAM device was fabricated using tantalum oxide (TaOx) as a resistive switching insulating oxide layer, which was sandwiched between two conducting electrodes, namely Ag and ITO. RF magnetron sputtering was used to deposit the insulating layer of TaOx at room temperature on the ITO substrate. Further, X-ray reflectivity and hard X-ray photoelectron spectroscopy analyses were conducted to find the thickness, roughness, and elemental composition of the deposited TaOx films. Using a semiconductor analyzer, the RRAM cell's first DC switching characteristics were determined. The data acquired exhibited a resistance ratio (RHRS/RLRS) of 120 showing a good distinction between the two-resistance states. Additionally, a thorough investigation was conducted to examine the electrical conduction mechanism occurring inside the fabricated RRAM device. [ABSTRACT FROM AUTHOR]

This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the SPICE simulator. Various performance parameters such as power consumption, power delay‐product, energy‐delay product and impact of key circuit parameters [supply voltage (VDD), channel length (Lg), gate width (Wg), channel doping concentration (NA), oxide thickness (TOX), threshold voltage (VT) and carrier mobility (µo)] on the duration of trigger pulses have been studied in‐depth and performance parameters are compared with circuits already available in the literature. The proposed circuit produces trigger pulses of a minimum width of 191.3 ps at a nominal supply of 1.0 V with an average power consumption of 160 nW. The width of the trigger pulses can be varied from 191.3 to 457.2 ps using an external control from 1.0 to 0.7 V, respectively, at 16 nm technology node. [ABSTRACT FROM AUTHOR]

This research work explores various circuit-level design techniques to identify the best technique suitable for low power circuit design. To establish a proper performance comparison, reported techniques are implemented in a transmission gate-based carry skip adder circuit @ 22-nm technology node. Results obtained demonstrate that the multi-threshold CMOS technique offers the best performance under the given conditions. Further, a novel modified hybrid circuit design technique is also proposed in this paper. To validate the proposed design technique, performance metrics of the carry-skip adder circuit implemented using the proposed hybrid technique and other low power circuit design techniques are compared. Obtained results establish that the proposed technique offers improvement in terms of propagation delay (TP), average power dissipation (PAVG), power delay product (PDP) and leakage power (LP), when compared with its counterpart at a supply voltage of 0.4 V. [ABSTRACT FROM AUTHOR]

Phase transform properties of Indium Selenide (In2Se3) based Random Access Memory (RAM) have been explored in this paper. Phase change random access memory (PCRAM) is an attractive solid-state nonvolatile memory that possesses potential to meet various current technology demands of memory design. Already reported PCRAM models are mainly based upon Germanium-Antimony-Tellurium (Ge2Sb2Te5 or GST) materials as their prime constituents. However, PCRAM using GST material lacks some important memory attributes required for memory elements such as larger resistance margin between the highly resistive amorphous and highly conductive crystalline states in phase change materials. This paper investigates various electrical and compositional properties of the Indium Selenide (In2Se3)material and also draws comparison with its counterpartmainly focusing on phase transformproperties. To achieve this goal, a SPICEmodel of In2Se3 based PCRAM model has been reported in this work. The reported model has been also validated to act as a memory cell by associating it with a read/write circuit proposed in this work. Simulation results demonstrate impressive retentivity and low power consumption by requiring a set pulse of 208 μA for a duration of 100 μs to set the PCRAM in crystalline state. Similarly, a reset pulse of 11.7 μA for a duration of 20 ns can set the PCRAM in amorphous state. Modeling of In2Se3 based PCRAM has been done in Verilog-A and simulation results have been extensively verified using SPICE simulator. [ABSTRACT FROM AUTHOR]

This study proposes a spintronic based compact tunable nano‐sized RF oscillator. The proposed design provides parametric performance improvement as compared with the designs already reported in literature. This design also offers higher operating frequency up to range of several GHz, which can be tuned by a DC bias current. The proposed magnetic tunnel junction‐spin torque oscillators (MTJ‐STO) model overcomes the limitation of low output power which is prime issue in spin torque oscillators (STOs). This is achieved by employing multi‐stage amplifier with impedance matching stages. In addition to that, mutual phase locking mechanism of STOs is introduced to act as a remedy for broadening of the spectrum linewidth, which is a critical issue in traditional oscillators. The hybrid model presented in this study contains spin torque based MTJ, which is compatible with CMOS technology. The modelling of proposed circuit has been done in Verilog‐A and simulation results have been verified using HSPICE. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient and robust design of content addressable memory (CAM) system. Design metrics, such as search time, power dissipation, power-delay product (PDP), and energy-delay product (EDP), of the proposed design are compared with those of previously reported CAM cell found in the literature. CAM cell presented in this paper offers $2.589\times $ improvement in search time, $2.725\times $ improvement in PDP, and $2.729\times $ improvement in EDP for mismatch 1 at 700 mV. It exhibits $2.257\times $ improvement in search time, $2.38\times $ improvement in PDP, and $2.389\times $ improvement in EDP for mismatch 0 at 700 mV. The proposed CAM cell also proves its efficiency in terms of power consumption, which is one of the most concerned design issues. It offers $1.0526\times $ improvement in power consumption for mismatch 1 and $1.054\times $ improvement in power consumption for mismatch 0. The proposed CAM cell is also analyzed to investigate the impact of tunneling magnetoresistance variations on power consumption, PDP, EDP, search time, and search-time variability. In addition, this paper also proposes an efficient match line sensing scheme for the proposed CAM cell. [ABSTRACT FROM PUBLISHER]

This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE. [ABSTRACT FROM AUTHOR]

This paper presents an approach for automatic segmentation of cardiac events from non-invasive sounds recordings, without the need of having an auxiliary signal reference. In addition, methods are proposed to subsequently differentiate cardiac events which correspond to normal cardiac cycles, from those which are due to abnormal activity of the heart. The detection of abnormal sounds is based on a model built with parameters which are obtained following feature extraction from those segments that were previously identified as normal fundamental heart sounds. The proposed algorithm achieved a sensitivity of 91.79% and 89.23% for the identification of normal fundamental, S 1 and S 2 sounds, and a true positive (TP) rate of 81.48% for abnormal additional sounds. These results were obtained using the PASCAL Classifying Heart Sounds challenge (CHSC) database.