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The capability of Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) to operate as a sharp logic switch is demonstrated in advanced FD-SOI (Fully Depleted SOI) technology. The operation mechanism is band-modulation which enables remarkable DC performance in terms of ON/OFF current ratio and sharp switch (~1 mV/decade). Z2-FETs have successfully been used for ESD protection and capacitorless DRAM memory, but the presence of an inherent hysteresis has handicapped so far logic applications. However, this letter shows that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. The sharpness of the switch depends on device parameters, bias and speed of operation. Systematic experiments compare the performance of Z2-FETs with dual or single ground-planes. [ABSTRACT FROM AUTHOR]

2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. [ABSTRACT FROM AUTHOR]

The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions. [ABSTRACT FROM AUTHOR]

A band-modulation device with a free top surface, named Z 3 -FET (Zero front-gate, Zero swing slope and Zero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technology, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is controlled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such as sharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. We explore several variants (thin and thick silicon or SiGe body) and show promising results in terms of high current, switching performance and ESD capability with relatively low back-gate and drain bias operation. [ABSTRACT FROM AUTHOR]

Abstract: A measurement setup for the characterization of very-fast transient responses in the CDM time domain is described in this paper. Experimental results are demonstrated on STI and gated diodes with a guard ring in a 65nm and 130nm CMOS technology. The superior behavior of gated diodes during triggering is highlighted. [Copyright &y& Elsevier]

Abstract: In this work, the use of the Z2-FET (Zero subthreshold swing and Zero impact ionization FET) for Electro-Static Discharge (ESD) protections is demonstrated. The device, fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator technology, features an extremely sharp off-on switch and an adjustable triggering voltage (Vt 1). The principle of operation, relying on the modulation of electron and hole injection barriers, is reviewed. The impact of process modules and design parameters on electrical characteristics is analyzed with TCAD simulations, showing that very low leakage current (Ileak ) and triggering capability adapted to local protection schemes are achievable. Experimental results validate the possible use of this device as an ESD protection in the 28nm FDSOI technology. [Copyright &y& Elsevier]