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In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC- $n$ LC, word-line batch score modulation programming, and SCB schemes. [ABSTRACT FROM AUTHOR]

Although multiple-level-cell (MLC) STT-RAM increases data density, it suffers from the two-step transition (TT) issue. It is because hard domain and soft domain of an MLC STT-RAM cell cannot be flipped to the opposite magnetization direction at the same time. Thus, the soft domain has to be flipped twice to the opposite magnetization direction of the hard domain. The TT problem hurts the lifetime of MLC STT-RAM due to additional flips on soft domains. To mitigate the TT problem of MLC STT-RAM, we propose an alternative encoding scheme (AES) to reduce the occurrence of TTs. AES utilizes the encoding method to eliminate most TTs and distributes unavoidable TTs among cells evenly to improve the lifetime of MLC STT-RAM cache. The experimental results showed that the proposed scheme achieved a great lifetime improvement than the related work. [ABSTRACT FROM AUTHOR]

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.jss.2006.03.023 Byline: Wan-Chen Lu (a), Jen-Wei Hsieh (b), Wei-Kuan Shih (a), Tei-Wei Kuo (b) Keywords: Real-time systems; Schedulability analysis; Periodic tasks; Fixed-priority preemptive scheduling Abstract: Real-time scheduling for task sets has been studied, and the corresponding schedulability analysis has been developed. Due to the considerable overheads required to precisely analyze the schedulability of a task set (referred to as exact schedulability analysis), the trade-off between precision and efficiency is widely studied. Many efficient but imprecise (i.e., sufficient but not necessary) analyses are discussed in the literature. However, how to precisely and efficiently analyze the schedulability of task sets remains an important issue. The Audsley's Algorithm was shown to be effective in exact schedulability analysis for task sets under rate-monotonic scheduling (one of the optimal fixed-priority scheduling algorithms). This paper focuses on reducing the runtime overhead of the Audsley's Algorithm. By properly partitioning a task set into two subsets and differently treating these two subsets during each iteration, the number of iterations required for analyzing the schedulability of the task set can be significantly reduced. The capability of the proposed algorithm was evaluated and compared to related works, which revealed up to a 55.5% saving in the runtime overhead for the Audsley's Algorithm when the system was under a heavy load. Author Affiliation: (a) Department of Computer Science, National Tsing Hua University, 101, Kuang Fu Road, Hsinchu 300, Taiwan, ROC (b) Department of Computer Science and Information Engineering, National Taiwan University, Taipei 106, Taiwan, ROC Article History: Received 11 July 2005; Revised 16 March 2006; Accepted 18 March 2006

With the emergence of big data era, NoSQL key-value database is considered as a promising candidate for replacing relational database management system (RDBMS). As cost per GB of flash memory is getting closer to HDD, high performance solid state drive (SSD) is regarded as the best substitute of HDD. However, there are still some issues that need to be taken into consideration. et al. have reported that applying key-value store to SSD with conventional FTL would incur internal fragmentation and further cause the degradation of device lifespan. Although they proposed KVFTL to deal with the above issues, their work gave rise to the read amplification problem. In this article, we investigate the root cause of the read amplification problem and propose elegantly measured tanner FTL (EMT-FTL) to mitigate internal fragmentation and read amplification with acceptable memory overhead. Different from KVFTL that slices a variable-sized value into multiple partitions (up to 20) of different sizes and manages them as a linked chain, EMT-FTL slices a value into 16 KiB full partitions with its remaining bytes treated as a fragment partition and appended to the fragment buffer. For a 64 GiB SSD with 16 KiB pages, the overall memory usage of EMT-FTL is only 8.81% of KVFTL. The experiments showed that EMT-FTL achieved almost the optimal space utilization as KVFTL did under most of traces and averagely improved the get performance by 78.57% (compared with KVFTL) under the traces with request sizes ranging from 1 byte to 16 KiB. [ABSTRACT FROM AUTHOR]

Spin-transfer torque RAM (STT-RAM) is an emerging non-volatile memory that has been recognized as the potential candidate to replace SRAM. Compared with SRAM, STT-RAM has advantages of non-volatility, zero leakage power, and higher density. To further improve data density, multi-level cell (MLC) STT-RAM that can store two bits per cell has been proposed. However, writing hard bit of a cell would write its soft bit to the same value as well, which complicates the write operation of MLC STT-RAM. Although two-step transition (TT) is usually adopted to ensure the data correctness during a write operation, it incurs overhead of additional energy consumption and performance degradation. In this article, we propose the two-step elimination (TSE) scheme to eliminate TTs while ensure data integrity. By flipping hard bits of the cells that suffered from TTs, the TSE scheme could reduce TTs to soft transitions (STs) or zero transitions (ZTs), which incur much less overhead than TTs. To keep track of the flipped cells effectively, 6-bit TSE tag is introduced. We exploit tag reversing and advanced mode of the TSE scheme to further improve the performance. The experimental results showed that our scheme could reduce 61 percent TTs and achieve significant lifetime improvement, compared with conventional MLC STT-RAM (CMLC) scheme. [ABSTRACT FROM AUTHOR]

As flash memory technology has been scaled down to 1x nm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this article, we propose multi-level retention-time queues with a management scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues could effectively separate data with different update frequencies. There are three challenge issues for a proper design: (1) Since access pattern might change from time to time, a technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. (2) Another technical issue is how to refresh each retention-time queue in time to guarantee data integrity. (3) Since blocks resided in different retention-time queue would suffer from different level of wearing, the third technical issue is how to estimate wearing status of flash-memory blocks in an effective and efficient manner to achieve wear leveling. In our scheme, data allocator, multi-level refresh module, garbage collector, and wear leveler are introduced to deal with these technical issues. Based on our experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme. [ABSTRACT FROM AUTHOR]

In recent years, flash memory has been widely used in embedded systems, portable devices, and high-performance storage products due to its nonvolatility, shock resistance, low power consumption, and high performance natures. To reduce the product cost, multi-level-cell (MLC) flash memory has been proposed; compared with the traditional single-level-cell (SLC) flash memory that only stores one bit of data per cell, each MLC cell can store two or more bits of data. Thus MLC can achieve a larger capacity and reduce the cost per unit. However, MLC also suffers from the degradation in both performance and reliability. In this paper, we try to enhance the reliability and reduce the product cost of flash-memory-based solid-state drive (SSD) from a totally different perspective. We propose the half-level-cell (HLC) scheme to manage and reuse the worn-out space in SSD; through our management scheme, the system can treat two bad pages as a normal page without sacrificing performance and reliability. The proposed scheme is purely on software/firmware-level, thus there is no need to change the hardware. The experiment results show that the lifetime of SSD with our proposed HLC scheme can be extended to 50.56% under the Windows workload and up to 65.45% under the multimedia workload. When we apply the HLC scheme to flash-memory cache of hybrid storage systems, the response time can be improved up to 20.57%. [ABSTRACT FROM AUTHOR]

In recent years, multi-level cell flash memory (MLC) has been widely adopted in solid state drives (SSD’s) as the major storage medium due to its lower cost and higher density, compared with single-level cell flash memory (SLC). However, MLC has reliability concerns since it has lower endurance and higher disturb failure rate. Researchers thus proposed SLC/MLC hybrid SSD to exploit the advantages of SLC and MLC by separating frequently updated data in SLC and seldom modified data in MLC. In this paper, we propose an adaptive error correction code (ECC) scheme with four ECC levels to enhance the reliability of SSD’s. Different from past researches, SLC is dedicated for the management of ECC, not for the user data. Since ECC is maintained in the data area of SLC (2 KB), rather than the spare area of MLC (128 Bytes), ECC capability is no longer confined by the limited size of the spare area. With adaptive management, ECC capability for a page would be upgraded whenever the current ECC cannot guarantee its reliability. A quantitative analysis is conducted to explore the impacts of different settings. The experiment results show that the lifetime of SSD can be extended by 318 percent for the trace of OLTP applications with our adaptive ECC scheme. [ABSTRACT FROM PUBLISHER]

DRAM is widely adopted as a cache for secondary storage due to its small access latency. Compared with DRAM, PRAM draws a lot of attention recently, since it provides higher density and has no need to refresh the capacitor charge periodically. The non-volatile nature of PRAM can even reduce compulsory miss, which cannot be avoided by DRAM cache. However, PRAM cache cannot replace DRAM cache due to its endurance issue. Thus DRAM/PRAM hybrid cache becomes a good alternative for traditional DRAM cache. Least recently used (LRU) replacement algorithm and CLOCK-Pro algorithm work well for traditional DRAM cache. But these algorithms shall not be directly applied to DRAM/PRAM hybrid cache since the characteristics of PRAM are not considered. This paper proposed a double circular caching scheme (DCCS) to manage DRAM/PRAM hybrid cache. In our scheme, cached data migrate between DRAM cache and PRAM cache adaptively to achieve good hit ratio while frequent writes to PRAM cache are avoided for endurance concern. The experimental results showed that our scheme can reduce up to 87.10 percent PRAM write accesses for read-intensive access pattern and up to 44.90 percent energy consumption for write-intensive access pattern, compared with other caching schemes. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel multi-version B^+-tree index structure, called block-based multi-version B^+-tree ( BbMVBT), for indexing multi-versions of data items in an embedded multi-version database (EMVDB ) on flash memory. An EMVDB needs to support streams of update transactions and version-range queries to access different versions of data items maintained in the database. In BbMVBT, the index is divided into two levels. At the higher level, a multi-version index is maintained for keeping successive versions of each data item. These versions are allocated consecutively in a version block. At the lower level, a version array is used to search for a specific data version within a version block. With the reduced index structure of BbMVBT, the overhead for managing the index in processing update operations can be greatly reduced. At the same time, BbMVBT can also greatly reduce the number of accesses to the index in processing version-range queries. To ensure sufficient free blocks for creating version blocks for efficient execution of BbMVBT, in this paper, we also discuss how to perform garbage collection using the purging-range queries for reclaiming “old” versions of data items and their associated entries in the index nodes. Analysis of the performance of BbMVBT is presented and verified with performance studies using both synthetic and real workloads. The performance results illustrate that BbMVBT can significantly improve the read and write performance to the multi-version index as compared with MVBT even though the sizes of the version blocks are not large. [ABSTRACT FROM PUBLISHER]

Several excellent researches have been proposed to improve the performance of solid-state drives (SSDs) by exploiting I/O parallelism of multi-channel architecture. However, these researches do not fully explore the internal parallelism and do not take wear leveling into consideration. In this paper, I/O performance is further improved by interleaving requests in channel level and striping sub-requests in plane level. A wear-leveling-aware distributed garbage collector is proposed to improve SSD lifetime and reclamation efficiency. To balance the utilization of user space among all channels, data migration is performed implicitly during channel selection and explicitly during garbage collection. To the best of our knowledge, this is the first paper on the design of distributed garbage collector for multi-channel flash-memory storage system. The experimental results showed that the proposed scheme can achieve good wear leveling and improve the overall performance by 34% for the Windows workload, 56.5% for the Linux workload, 88.4% for the multimedia workload, and 9.3% for the on-line transaction processing (OLTP) workload under the two-die-two-plane architecture, compared with the related work. [ABSTRACT FROM AUTHOR]

In recent years, multilevel cell Flash memory (MLC), which stores two or more bits per cell, has gradually replaced single-level cell flash memory due to its lower cost and higher density. However, MLC also brings new constraints, i.e., no partial programming and sequential page writes within a block, to the management. This paper proposes a virtual log-block-based hybrid-mapping scheme, referred to as virtually associative sector translation (VAST), for MLC storage systems. Unlike traditional hybrid-mapping schemes, VAST is a combination of block-level and segment-level mappings and manages log blocks in a flexible manner. The goals of our research are to avoid timeout by decreasing dummy-page writes, to get a better response time by decreasing live-page copies, and to prolong the life span of flash memory by decreasing total block erasures. Our trace-driven simulation shows that VAST could reduce up to 90% of dummy-page writes, 22%–52% of live-page copies, and 55%–83% of block erasures, compared to well-known hybrid-mapping schemes. [ABSTRACT FROM AUTHOR]