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An analog baseband (ABB) spectrum sensing circuit is proposed for fast spectrum sensing. Contrast to the conventional RF scanner where it takes a relatively long period to detect channel and interference condition by sequentially controlling the center frequency of the filter, the proposed ABB circuit can scan it at a time using different bandwidths of low-pass filters with an almost equal out-of-band attenuation slope to sense the powers and frequencies of channel and interference. The ABB circuit is composed of two chains of five cascaded real and complex low-pass filters. The cut-off frequencies of five cascaded low-pass filters are set to be 10, 8, 6, 4 and 2 MHz respectively, regarding the channel bandwidth of 2 MHz. The orders of the five filters are optimized to be $4^{\mathrm{ th}}$ , $4^{\mathrm{ th}}$ , $3^{\mathrm{ rd}}$ , $2^{\mathrm{ nd}}$ , and $2^{\mathrm{ nd}}$ order respectively to make the rejected out-of-band power same for each filter for accurate detection. The filter core is designed on the basis of a flipped voltage follower and a super source follower for a low power dissipation and a high linearity, and the low power technique for implementing high-order filter is newly proposed in the design of filter chain. The measured frequency response at each output of the filter chain was almost the same to the simulation result. The measurement results show a noise figure (NF) of 19.2 dB, 22.1 dB, 24.8 dB, 25.1 dB, and 27 dB for each filters, and an in-band input-referred third-order intercept point (IIP3) of 9.2 dBm, 7.2 dBm, and 15.7 dBm at the output of $1^{\mathrm{ st}}$ , $3^{\mathrm{ rd}}$ , and last stages. The total power consumption of the filter chain is 10.4 mW from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13- $\mu \text{m}$ CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance ($g_{m}$) ratio of the same types of nMOS transistors, its power gain ($S_{21}$) and NF are quite roust over PVT variations. In experiments, it showed $S_{21}$ of 14 dB and NF of 4 dB with an input return loss ($S_{11}$) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08–1.32 V) and temperature variation ($- 20\,\,^{\circ }\text {C} \sim +80 \,\,^{\circ }\text{C}$), the worst variations in $S_{21}$ and NF were approximately 1.4 and 1.1 dB, respectively. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a low‐power low‐noise complementary metal‐oxide semiconductor (CMOS) receiver RF front‐end (RFFE) that employs a current‐reuse Q‐boosted resistive feedback low‐noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio‐communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common‐source LNA without using large on‐chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current‐reuse transconductor, in which a p‐channel metal‐oxide semiconductor (PMOS) transistor performs a current‐bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65‐nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm. [ABSTRACT FROM AUTHOR]

A 1.9-GHz single-stage differential stacked-FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32-μm 2.8-V thick-oxide MOSFETs in a 0.18-μm silicon-on-insulator CMOS process. The input cross-coupled stacked-FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked-FET power amplifier in sub-micrometer CMOS technology. With a 4-V supply voltage, the proposed power amplifier with an integrated output coupled-resonator balun showed a small-signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power-added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18- \mu\textm CMOS process for TV tuner applications. It shows a measured voltage gain (Av) of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than −20 dBm in the frequency range from 44 to 880 MHz. The baseband coefficient scaling and summation based on the current mirror ensure a third- and fifth-harmonic rejection ratio of over 45 dBc in measurement with high linearity performance. The power consumption of the proposed TV receiver front-end is 16.2 mW at a 1.8-V supply voltage. [ABSTRACT FROM PUBLISHER]

A dual-loop feedback broadband low-noise amplifier (LNA) employing second-order inter-modulation distortion (IMD2) cancellation is implemented in an 0.18- \mu \text m silicon-on-insulator (SOI) CMOS technology. The dual-loop feedback configuration stabilizes an input return loss ( S 11 ) of the LNA at the VHF low band around 50 MHz with small dc blocking capacitors. In order to achieve a second-order output-referred intercept point (OIP2) of greater than +50 dBm with reasonably low power consumption, all of the building blocks of the proposed LNA are designed to have a complementary configuration while the body-bias control technique is applied to the inverter-based resistive feedback amplifier. In addition, the peaking inductor is placed inside the feedback loop at the gate of the input transistor to enhance the bandwidth of the LNA. The designed LNA achieves a measured power gain ( S 21 ) of 10.1 dB, a noise figure (NF) of less than 4 dB, and an input return loss ( S 11 ) of greater than 10 dB over frequencies ranging from 50 MHz to 3 GHz. The measurements show a third-order output-referred intercept point (OIP3) of +17.8 dBm and an OIP2 of +53 dBm at 1 GHz. [ABSTRACT FROM PUBLISHER]

This paper reports a source follower-based active RC filter topology for RF front-ends in wideband systems. In the proposed active RC filter, the noise figure and bandwidth are improved through adopting the proposed sub-1 \Omega Z out source follower, which replaces the conventional operational amplifier-based unity gain buffer and through simply changing its location in the filter. Applying the proposed scheme to the conventional Sallen–Key filter also improves the stopband rejection performance. Furthermore, the proposed filter topology ultimately suppresses the DC offset voltage and flicker noise of the unity gain buffer, which is the only active circuit in the filter. The proposed biquad filter is implemented in 0.18 \mu\m CMOS and the measurements exhibit >26 dBm IIP3, +12 dBm input P 1dB, and <15 dB noise figure over 50–450 MHz of a 6 bit tunable frequency range. The proposed biquad filter consumes 14 mA from a 1.8 V supply and the chip occupies 1000\times500 \mu \m ^2. [ABSTRACT FROM PUBLISHER]

A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain–source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain–source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to +35 dBm with suitably low IL of less than 1 dB, and shows second- and third-order harmonic distortion of less than -45 dBm when a 1-GHz RF signal with a power of +35 dBm and a 2-GHz RF signal with a power of +33 dBm are applied. The proposed antenna switch consumes almost no static power. [ABSTRACT FROM PUBLISHER]

A highly linear LNA is implemented in a 0.18 µm SOI CMOS process for 1 GHz SAW-less receiver applications. To achieve lower noise figure (NF) than conventional simultaneous noise and input matching methods, a capacitive loading based simultaneous noise and input matching technique reducing the NF degradation coming from a lossy gate inductor has been devised. In addition, in order to improve both the 1 dB gain compression point (CP1dB) and the third-order intercept point (IP3) without sacrificing NF, a large-signal transconductance linearization method adopting body-bias control and complementary-superposition is proposed. The proposed LNA shows a measured input-referred CP1dB of 3 dBm, 1 dB desensitization point (B1dB) of 0 dBm and IB (in-band)-IIP3 of 22 dBm with gain of 10.7 dB and NF of 1.3 dB at 1 GHz while driving a 50 Ω load impedance. It draws 20 mA with a buffer stage from a 2.5 V supply voltage. [ABSTRACT FROM PUBLISHER]

A highly linear complementary source follower (CSF) feedback CMOS wideband LNA is implemented as a part of a highly linear receiver front end resilient to 0-dBm out-of-band blockers. Due to the linear feedback operation of the CSF, the proposed LNA greatly improves large-signal linearity performances compared to the conventional SF feedback LNA. The proposed feedback LNA shows an input P1dB close to 0 dBm while achieving an input reflection coefficient less than -10 dB, an average power gain of 10 dB, and a minimum noise figure of 3 dB. The power consumption is 18 mW at a 2-V supply voltage. [ABSTRACT FROM AUTHOR]

A wideband CMOS highly linear and low noise RF front-end including inductor-less wideband LNA, integrated passive tunable filter, harmonic rejection mixer (HRM), and loop-through amplifier (LTA) is proposed for universal tuners. The proposed inductor-less wideband LNA shows a gain range greater than 55 dB with fine gain step less than 0.5 dB while achieving higher linearity and lower noise figure (NF), as compared with the traditional resistive/active feedback LNA through a source follower (SF). The integrated tunable filter covers the entire VHF bands without dividing the frequency range by multiple filters. By adopting tunable filter and HRM simultaneously, the overall harmonic rejection ratio (HRR) of over 65 dBc is obtained. The active feedback LTA utilizing a complementary characteristic of NMOS and PMOS is proposed for supporting multiple tuner applications. The proposed RF front-end achieves a maximum voltage gain of 42 dB, a minimum NF of 4.7 dB, and CTB and CSO of under -60 dBc. The power consumption including the LTA is 144 mW at a 1.8 V supply and the chip area is 1.43 mm^2. [ABSTRACT FROM PUBLISHER]

A wideband active feedback single-to-differential (S-to-D) low-noise amplifier (LNA) for digital TV (DTV) tuners composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed to achieve low noise as well as to improve the linearity performances (IIP2 and IIP3) simultaneously. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. The differential mode operation of the voltage combiner reduces the second-order nonlinearity feedback, allowing us to improve both the IIP3 and IIP2 of the LNA at the same time. Two LNA design examples are presented to demonstrate usefulness of the proposed approach. The LNA I, by adopting a common source (CS) amplifier with a common gate, common source (CGCS) balun load as the S-to-D converter, is able to achieve a high gain and a low noise figure (NF) by increasing the loop gain. The LNA II using the differential amplifier with the ac-grounded second input terminal is designed for robust IIP2 to PVT variations. [ABSTRACT FROM AUTHOR]

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 μm CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2. [ABSTRACT FROM AUTHOR]

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

A stacked-FET linear 4-bit silicon-on-insulator (SOI) CMOS switched capacitor array is designed for use in tunable antenna matching circuits. A New biasing strategy without negative bias voltage is proposed to circumvent drawbacks such as digital switching noise and harmonics feed-through to the antenna. The proposed switched capacitor array shows almost identical power handling capability to that of the conventional version with negative bias voltage. Compared to other works in SOI or silicon-on-sapphire (SOS) technologies, it shows a comparable or better quality factor, tuning range, power handling capability, and harmonic distortion while consuming ultra low power. [ABSTRACT FROM PUBLISHER]

A CMOS self-tuned low noise amplifier (LNA) with single-to-differential function is presented. A tuned LNA with high-Q band-pass filtering is reconfigured to an oscillator simply by enabling a positive feedback buffer. Using the proposed LNA, an RF filter can be self-tuned without additional tone-generator circuits, and the calibration system is greatly simplified. By adopting a differential hybrid voltage buffer, differential imbalance is minimized. For a proof-of-concept, the proposed LNA is implemented using a 0.18 \mum CMOS process. The circuit operates in a tuning range of 0.8–1.5 GHz, while the error between oscillation and center frequency is less than 5%. A pass band gain of 26.7–30 dB, a noise figure (NF) of 3.9–4.3 dB, and an in/out band IIP3 of -9.9/+10.6 dBm are obtained. The LNA consumes 9 mA with 1.8 V supply. [ABSTRACT FROM PUBLISHER]

A CMOS broadband differential low noise amplifier (LNA) employing noise and third order intermodulation (IM3) distortion cancellation has been designed using a 0.13 \mum CMOS process for mobile TV tuners. By combining a common gate amplifier with a common source amplifier through a current mirror, a high gain due to the additional current amplification and a low noise figure (NF) due to the thermal noise cancellation can be achieved with low power consumption without degrading the input matching. To improve the linearity with low power consumption, a multiple gated transistor technique for canceling the IM3 distortion is adopted. The proposed LNA has a maximum gain of 14.5 dB, an averaged NF of 3.6 dB, an IIP3 of 3 dBm, an IIP2 of 38 dBm, and an \vert S 11 \vert lower than -9 ~dB in a frequency range from 72 to 850 MHz. The power consumption is 9.6 mW at a 1.2 V supply voltage and the chip area is 0.08 mm^2. [ABSTRACT FROM PUBLISHER]

A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration. [ABSTRACT FROM AUTHOR]

Corrections to the article "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization" by Bum-Kyum Kim and colleagues are presented.

Biointegrated electronics have been investigated for various healthcare applications which can introduce biomedical systems into the human body. Silicon-based semiconductors perform significant roles of nerve stimulation, signal analysis, and wireless communication in implantable electronics. However, the current large-scale integration (LSI) chips have limitations in in vivo devices due to their rigid and bulky properties. This paper describes in vivo ultrathin silicon-based liquid crystal polymer (LCP) monolithically encapsulated flexible radio frequency integrated circuits (RFICs) for medical wireless communication. The mechanical stability of the LCP encapsulation is supported by finite element analysis simulation. In vivo electrical reliability and bioaffinity of the LCP monoencapsulated RFIC devices are confirmed in rats. In vitro accelerated soak tests are performed with Arrhenius method to estimate the lifetime of LCP monoencapsulated RFICs in a live body. The work could provide an approach to flexible LSI in biointegrated electronics such as an artificial retina and wireless body sensor networks.