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Abstract Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary.

Abstract To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

Abstract To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm2, which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (Ron). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.

GaN vertical PiN diodes with different anode thicknesses were fabricated on three native GaN wafers with the same p-layer doping concentrations, and planar hybrid edge termination. The breakdown behavior in terms of the breakdown voltage and the electroluminescence were studied as functions of the anode thickness. A repeatable avalanche breakdown and highest breakdown voltage were measured with the thinnest anode of 300 nm and with the thinnest edge termination region. This indicates the efficacy of the nitrogen-implanted hybrid edge termination design that comprises of junction termination and guard rings hybrid design. As the anode thickness increases, the edge termination thickness increases, and the devices exhibit lower breakdown voltages and less robust breakdown characteristics, often destructive. From this study, we also conclude that a very high p-layer doping of 2 × 1019 cm−3 is not s practical doping level, because it is too sensitive to the edge termination thickness.

Vertical heterojunction p-CuI/n-Ga2O3 diodes were fabricated on commercial β-Ga2O3 substrates using the reaction of epitaxially-sputtered Cu with natural I2 vapor at room temperature followed by either a high temperature I2 gas reaction or an I2 solution treatment to remove iodine vacancies. Results show that using an epitaxially-oriented over a polycrystalline Cu layer produces larger and more strongly bonded CuI crystals. Hall and current–voltage measurements support rectifying behavior consistent with p-CuI/n-Ga2O3 heterojunction characteristics including 8 orders of magnitude Ion/Ioff ratio and an ideality factor of 1.37 measured on the sample with the lowest concentration of iodine vacancies. [ABSTRACT FROM AUTHOR]