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We report a simple metal-insulator-metal (MIM)-type selection device that can alleviate the sneak current path in cross-point arrays. By connecting a nanometer-scale Pt/TiO2/TiN selection device to a Pt/TiO2-x/TiO2/W resistive random access memory (RRAM), we could significantly reduce read disturbance from unselected memory cells. This selection device could be easily integrated into an RRAM device, in which it suppressed the sneak current and significantly improved the readout margin compared to that obtained for an RRAM not using a selection device. The introduction of this MIM device can fulfill the requirement for an appropriate selection device for bipolar-type RRAM cross-point applications. [ABSTRACT FROM AUTHOR]

We investigated the electronic properties of ZnO nanowire combined with the scaled high-k Al2O3 dielectrics using metal-oxide-semiconductor and field effect transistor (FET) device structures. We found that Al2O3 dielectric material can significantly reduce leakage currents when the applied voltage was restricted less than the transition voltage of direct tunneling to Fowler–Nordheim tunneling. The ZnO nanowire FETs with Al2O3 dielectrics exhibited the increase in electrical conductance, transconductance, and mobility and the threshold voltage shifted to the negative gate bias direction with decreasing Al2O3 dielectric layer thickness. [ABSTRACT FROM AUTHOR]

Abstract: The charge trapping and positive bias temperature instability (PBTI) are investigated at different post deposition annealing conditions (PDA) in HfO2 nMOSFET. Pulse based measurements (Pulsed Id-Vg and “Pulse on the fly”) are performed to characterize charge trapping effect. Compared with NH3 PDA, the NH3 +O2 PDA shows significant reduction of charge trap sites in HfO2, which causes the improvement of device performance and reliability. The significant improvement after additional annealing can be explained by the passivation of oxygen vacancies in HfO2. [Copyright &y& Elsevier]

A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type HfO\rm{x}-based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations using a current crowding effect This model is a semiempirical model that can simultaneously match both dc and ac characteristics of HfO\rm{x}-based ReRAM devices. [ABSTRACT FROM PUBLISHER]

We propose a selector-less Pr0.7Ca0.3MnO3 (PCMO) based resistive-switching RAM (RRAM) for high-density cross-point memory array applications. First, we investigate the inhomogeneous barrier with an effective barrier height ( Φeff), i.e., self-formed Schottky barrier. In addition, a scalable 4F2 selector-less cross-point 1 kb RRAM array has been successfully fabricated, demonstrating set, reset, and read operation for high cell efficiency and high-density memory applications. (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In this letter, a strategy to minimize the error in lifetime projections using a positive bias temperature instability (PBTI) test has been proposed. Two distinctly different projection slopes were observed in a plot of time to failure versus oxide electric field. A small slope in the high-field region, which means weaker electric field dependence, led to an underestimation of lifetime. This result was attributed to a filled trap cluster at a specific trap energy level, locally reducing the oxide electric field. Thus, different lifetimes can be projected depending on stress bias. Maintaining a PBTI stress bias range below this trap energy level is recommended for accurate projections. [ABSTRACT FROM PUBLISHER]

In this letter, we propose a model based on noise analysis for the filamentary switching mechanism in resistance random access memory having \ZrOx/\HfOx bilayer stacks. From the noise analysis results, we concluded that the current flowing during high-resistance state can be described as a trap-assisted current that flows through traps. It has been hypothesized that these traps are the cause of the instability of device parameters. To validate this, the noise analysis results of large-area devices were compared with those of small-area devices. As a consequence, we improved the uniformity of device parameters. [ABSTRACT FROM AUTHOR]

We investigated the effect of scaling down the device area of \WOx resistive random-access memory (RRAM) devices on their switching characteristics. Device dimensions were successfully scaled down to 50 nm using a via-hole structure with additional \Al2\O3 sidewall process. As compared to the microscale devices, the nanoscale devices exhibited a distinct switching mechanism and better memory performance, such as improved switching uniformity, larger memory window, and stable endurance characteristics for up to \10^7 cycles. This improvement can be explained by a uniform interfacial switching mechanism in nanoscale device; this is in contrast with the defect-induced filamentary switching mechanism observed in microscale devices. In this way, the intrinsic switching properties of RRAMs were obtained by scaling down of the device area, indicating that RRAMs hold considerable promise for future applications. [ABSTRACT FROM AUTHOR]

We proposed a new set/reset operation scheme to improve the switching uniformity of filament-type resistive memory. By controlling the magnitude of the sweep voltage in the pulse-sweep mode at each set and reset operation, similar resistance of a conducting filament in a low-resistance state and a homogeneously dissolved conducting filament in high resistance state were obtained continuously. As compared with a normal operation scheme involving a fixed voltage, our new operation scheme exhibits dramatically improved switching uniformity. By combining the new operation scheme with a gradual reset operation, we successfully achieved a stable multibit operation. [ABSTRACT FROM PUBLISHER]

We report resistive switching in Pr0.7Ca0.3MnO3 (PCMO) devices using multilayer graphene (MLG) for nonvolatile memory applications. When MLG was used as a conducting electrode, PCMO device exhibited resistive switching with an on/off ratio of over two orders of magnitude and stable retention characteristics for over 104 s at 85 °C. Raman spectroscopy in both resistance states revealed increases in D and D′ peaks associated with defects and large shift in G peak position for high-resistance state. This was attributed to formation and dissolution of oxygenated graphene at the MLG/PCMO interface, resulting in resistive switching. [ABSTRACT FROM AUTHOR]

Improved switching uniformity and speed were demonstrated using a filament-type resistive memory. By using a gradual reset operation, a leaky high resistance, which has a smaller gap distance confirmed by C-AFM, was successfully obtained. The leaky high-resistance state shows significantly improved switching uniformity compared to the high-resistance state, which has a higher resistance than the leaky high-resistance state, because of the confinement of the randomly formed conducting filaments. A faster operation speed was achieved using the smaller gap distance. To confirm the improved switching speed, we monitored the real-time oscilloscope response. [ABSTRACT FROM AUTHOR]

We have investigated the bilayer structure of binary oxides such as HfOx and ZrOx for applications to resistance memory. The ZrOx/HfOx bilayer structure shows a lower reset current and operating voltage than an HfOx monolayer under dc sweep voltage. Furthermore, the bilayer structure exhibits a tight distribution of switching parameters, good switching endurance up to 105 cycles, and good data retention at 85 °C. The resistive switching mechanism of memory devices incorporating the ZrOx/HfOx bilayer structure can be attributed to the control of multiple conducting filaments through the occurrence of redox reactions at the tip of the localized filament. [ABSTRACT FROM AUTHOR]

We investigated advanced impurity trap memory (ITM) with atomic-scale Ti impurities on LaAlO3. Our ITM showed excellent memory characteristics, including a memory window (MW) of 5 V under +12 V/-10 V, ∼44% retained charge in 10 yr retention at 85 °C, and endurance without MW degradation up to 104 cycles. To understand the origins of these enhanced characteristics, we conducted various physical analyses. Our results confirmed that the incorporation of ultrathin LaAlO3, featuring both thermodynamic stability for diffusion barrier of Ti and favorable energy band structure together with high dielectric constant for bandgap engineering of tunnel oxide, is responsible for enhanced performance. [ABSTRACT FROM AUTHOR]

We investigated the generation and recovery process of traps in pMOSFETs under negative-bias temperature (NBT) stress by using pulsed and dc measurements. The behavior of generated traps was studied as a function of applied body bias (VB). The fast components induced with the application of a positive VB were independent of measurement time (tm), while the results from devices with no applied VB showed a strong dependence on tm. This suggests that the fast components of additional traps generated by a positive VB can be attributed to interface states (Nit) at the Si/SiO2 interface. Based on the results of recovery characteristics with an intentional measurement delay, the recovery of Nit is relatively slow, initiating on the scale of a few milliseconds. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (Nit) from that of oxide traps (Not) to NBTI behavior by varying the measurement time (tm) and the delay time (tR). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the Not in high-k dielectric was more responsible for the NBTI behavior than the Nit, but the contribution of Nit to NBTI increased as the stress continued because the generation rate of Nit was higher than that of Not. [ABSTRACT FROM AUTHOR]

The correlation between properties of the Si3N4/Al2O3 interface and retention degradation was investigated for metal-alumina-nitride-oxide-silicon-type flash memory devices. The intermixed region near the Si3N4/Al2O3 interface showed an oxygen deficiency, which was confirmed by the binding energy of Al and Si peaks from x-ray photoelectron spectroscopy analysis. This oxygen deficiency led to the enhancement of trap-assisted tunneling current. Additional ambient oxygen annealing can eliminate the oxygen deficiency at the intermixed region, which in turn can significantly reduce charge loss through the blocking oxide. With the aim of better memory characteristics, oxygen incorporation shows promise for future nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

We have investigated the effect of high-pressure deuterium oxide annealing (HPDOA) on metal-alumina-nitride-oxide-silicon-type flash memory device. HPDOA was performed in a high-pressure wet vapor ambient (N2:D2O=10 atm:2 atm) at 250 °C for 5 min. HPDOA devices achieved the improvements of blocking oxide quality as well as tunneling oxide/Si interface quality. The improvement of blocking oxide induced the lower charge loss through the blocking oxide, lower leakage current density, lower erase saturation level, and a larger memory window after the program/erase cycles. In addition, the presence of deuterium at the tunneling oxide/Si improved the interface quality by the formation of Si–D bonds. [ABSTRACT FROM AUTHOR]

A nonvolatile nanocrystal (NC) memory containing a ferritin core was fabricated. A ferritin monolayer was formed through a droplet evaporation technique. High-pressure hydrogen (HP-H2) annealing effectively reduced iron oxide (Fe2O3) to form conductive iron NC. In addition, HP-H2 annealing also improved memory characteristics by passivation of the interface states at Si/HfO2. The authors observed good memory characteristics, including fast program/erase (P/E) operation, a memory window of 1.75 V under ±6 V, and a stable memory window up to 104 s at 85 °C. [ABSTRACT FROM AUTHOR]

Scaling effects of In2O3 nanowire field effect transistors (FETs) were examined as a function of channel length. The channel length was varied from 1 μm to 20 nm by placing a conducting atomic force microscope tip on the In2O3 nanowire as a movable contact. The In2O3 nanowire FET exhibited a variety of channel-length dependent transfer characteristics in terms of the source-drain current, transconductance, threshold voltage, and mobility. Furthermore, the authors were able to extract the contact resistance and distinguish between apparent mobility and intrinsic mobility. The latter was corrected, taking into account the non-negligible contact resistance for short channel devices. [ABSTRACT FROM AUTHOR]

Al2O3 with a negative fixed charge prepared by atomic layer deposition has been reported to improve surface passivation properties for Si-solar cell applications. The high negative fixed charge at the SiO2/Al2O3 interface facilitates a low surface recombination velocity and a high effective lifetime, which result in greater performance. In this study, we adopted an effective method using a slant-etched sample with various thicknesses of SiO2 to estimate the charge densities of both the bulk and interface of Al2O3 deposited by atomic layer deposition. We found a direct correlation between lifetime and total charge density in Al2O3, which are strong functions of film thickness and annealing condition. [ABSTRACT FROM AUTHOR]

The device performance and reliability degradation of an n-type metal–oxide–semiconductor field-effect transistor (nMOSFET) that depend on the composition of a tantalum–silicon–nitride (TaSiN) electrode were investigated. Compared with a binary tantalum–nitride (TaN) gate electrode, nMOSFETs with ternary TaSiN electrodes showed the degradations of electron mobility and interface reliability. In addition, the electron mobility and interface reliability were significantly degraded by increasing the tantalum and silicon content in the TaSiN electrodes. By single pulsed drain current (pulsed Id–Vg) and charge pumping measurements, significantly increased number of charge trapping sites and interface traps were observed in nMOSFETs with ternary TaSiN electrodes. The degraded electrical properties of hafnium oxide (HfO2) can be explained by the TaSiN gate electrode/dielectric interaction during the high-temperature process. [ABSTRACT FROM AUTHOR]

We have investigated the effect of high-pressure oxygen annealing (HPOA) on metal–alumina–nitride–oxide–silicon (MANOS)-type flash memory devices. HPOA devices show significant improvement of retention characteristics at elevated temperatures under positive gate bias owing to the reduction of charge loss rate through the blocking oxide. Considering the improvement of electrical characteristics and the change in the Al chemical state, this was attributed to the effective removal of traps and the recovery of the stoichiometry of Al2O3 layer by oxygen passivation. We also confirmed this effect in a Si–Al2O3–Pt capacitor. As a result, we consider that HPOA could be a crucial process for future MANOS-type memory devices. [ABSTRACT FROM AUTHOR]

We demonstrated analog memory, synaptic plasticity, and a spike-timing-dependent plasticity (STDP) function with a nanoscale titanium oxide bilayer resistive switching device with a simple fabrication process and good yield uniformity. We confirmed the multilevel conductance and analog memory characteristics as well as the uniformity and separated states for the accuracy of conductance change. Finally, STDP and a biological triple model were analyzed to demonstrate the potential of titanium oxide bilayer resistive switching device as synapses in neuromorphic devices. By developing a simple resistive switching device that can emulate a synaptic function, the unique characteristics of synapses in the brain, e.g. combined memory and computing in one synapse and adaptation to the outside environment, were successfully demonstrated in a solid state device.

We demonstrated the nonvolatile memory functionality of ZnO nanowire field effect transistors (FETs) using mobile protons that are generated by high-pressure hydrogen annealing (HPHA) at relatively low temperature (400 °C). These ZnO nanowire devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We show that the memory characteristics are attributed to the movement of protons between the Si/SiO(2) interface and the SiO(2)/ZnO nanowire interface by the applied gate electric field. The memory mechanism is explained in terms of the tuning of interface properties, such as effective electric field, surface charge density, and surface barrier potential due to the movement of protons in the SiO(2) layer, consistent with the UV photoresponse characteristics of nanowire memory devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials.

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 microm(2) to 200 x 200 nm(2). From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I(ON)/I(OFF) approximately 10(4)), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10,000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.