Search

Augmented reality (AR) technology is expanding into the restaurant industry, yet the use of AR menus has not been investigated yet. The purpose of this research is to study consumers’ perceptions of the use of AR menus in restaurants. A research model grounded in the Technology Acceptance Model (TAM) was used for the study. After 368 responses were collected through an online self-administered survey, multiple regression analyses were performed to explore the impact of factors on customer intention. The results of the study indicated that perceived usefulness, perceived innovativeness, subjective norm, perceived enjoyment, and perceived benefit influenced customer intention. In addition, it was found that there are gender differences in consumer intention. Managerial and theoretical implications are discussed; limitations and recommendations for future study are also provided. [ABSTRACT FROM AUTHOR]

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively. [ABSTRACT FROM AUTHOR]

A sizable fraction of granule cells convey information about the expectation of reward, with different populations responding to reward delivery, anticipation and omission, with some responses evolving over time with learning. Reward response in granule cells Classical theories suggest that granule cells in the cerebellum carry sensory and motor signals, enabling downstream Purkinje cells to sense fine contextual changes relating to movement. Using two-photon calcium imaging in behaving mice, Liqun Luo and colleagues also show that a sizable fraction of granule cells convey information about the expectation of reward. Different populations responded to reward delivery, anticipation and omission and some responses evolved over time with learning. The discovery of reward-related signals in granule cells has implications for both models of sensorimotor learning and of cognitive processing in the cerebellum. The human brain contains approximately 60 billion cerebellar granule cells.sup.1, which outnumber all other brain neurons combined. Classical theories posit that a large, diverse population of granule cells allows for highly detailed representations of sensorimotor context, enabling downstream Purkinje cells to sense fine contextual changes.sup.2,3,4,5,6. Although evidence suggests a role for the cerebellum in cognition.sup.7,8,9,10, granule cells are known to encode only sensory.sup.11,12,13 and motor.sup.14 context. Here, using two-photon calcium imaging in behaving mice, we show that granule cells convey information about the expectation of reward. Mice initiated voluntary forelimb movements for delayed sugar-water reward. Some granule cells responded preferentially to reward or reward omission, whereas others selectively encoded reward anticipation. Reward responses were not restricted to forelimb movement, as a Pavlovian task evoked similar responses. Compared to predictable rewards, unexpected rewards elicited markedly different granule cell activity despite identical stimuli and licking responses. In both tasks, reward signals were widespread throughout multiple cerebellar lobules. Tracking the same granule cells over several days of learning revealed that cells with reward-anticipating responses emerged from those that responded at the start of learning to reward delivery, whereas reward-omission responses grew stronger as learning progressed. The discovery of predictive, non-sensorimotor encoding in granule cells is a major departure from the current understanding of these neurons and markedly enriches the contextual information available to postsynaptic Purkinje cells, with important implications for cognitive processing in the cerebellum., Author(s): Mark J. Wagner [sup.1] , Tony Hyun Kim [sup.1] [sup.2] , Joan Savall [sup.1] , Mark J. Schnitzer [sup.1] [sup.3] , Liqun Luo [sup.1] Author Affiliations: (1) Department of [...]

This study aimed to study factors affecting hospitality and tourism student satisfaction and their intention to stay in the program. A model with nine factors was proposed and tested. The results showed that curriculum, hospitality & tourism degree commitment, student life, self-efficacy, and goals positively affect undergraduate student satisfaction with the program whereas curriculum, hospitality & tourism degree commitment, student life, and financial support affect their intention to stay in the program. This study also tested all hypothesized relationships to see if those relationships differ between underclassmen and upperclassmen. Implications for hospitality and tourism educators and administrators are provided. [ABSTRACT FROM AUTHOR]

With the adverse effects of the COVID-19 pandemic widely visible in the event industry, event organizers face challenges regarding customer retention in the form of return visits. Because event revisit intention is crucial to predicting event attendees' behavior, this study attempts to examine the likelihood of return for customers who have prior event (state fair) experience. Drawing from previous studies on event-related hazards and safety risks, our proposed framework suggests that a certain type of trust (i.e., social trust and confidence) reduces perceived risk, leading to increased event revisit intention in a time of pandemic. To test hypothesized relationships among trust, perceived risk, and event revisit intention, consumer information was gathered through Amazon's Mechanical Turk crowdsourcing platform. Key findings that emerge include the fact that trust in events is a strong predictor of event revisit intention, while perceived risk mediates the relationship between trust and revisit intention, albeit weakly. These results offer event organizers insights into how to enhance revisit intention in the face of health risks and ongoing uncertainty. [ABSTRACT FROM AUTHOR]

In this work, we present a novel 8T static random access memory (SRAM)-based compute-in-memory (CIM) macro for processing neural networks with high energy efficiency. The proposed 8T bitcell is free from disturb issues thanks to the decoupled read channels by adding two extra transistors to the standard 6T bitcell. A 128 $\times $ 128 8T SRAM array offers massively parallel binary multiply and accumulate (MAC) operations with 64 $\times $ binary inputs (0/1) and 64 $\times $ 128 binary weights (+1/–1). After parallel MAC operations, 128 column-based neurons generate 128 $\times $ 1–5 bit outputs in parallel. The proposed column-based neuron comprises 64 $\times $ bitcells for dot-product, 32 $\times $ bitcells for analog-to-digital converter (ADC), and 32 $\times $ bitcells for offset calibration. The column ADC with 32 $\times $ replica SRAM bitcells converts the analog MAC results (i.e., a differential read bitline (RBL/RBLb) voltage) to the 1–5 bit output code by sweeping their reference levels in 1–31 cycles (i.e., $2^{N}$ –1 cycles for $N$ -bit ADC). The measured linearity results [differential nonlinearity (DNL) and integral nonlinearity (INL)] are +0.314/–0.256 least significant bit (LSB) and + 0.27/–0.116 LSB, respectively, after offset calibration. The simulated image classification results are 96.37% for Mixed National Institute of Standards and Technology database (MNIST) using a multi-layer perceptron (MLP) with two hidden layers, 87.1%/82.66% for CIFAR-10 using VGG-like/ResNet-18 convolutional neural networks (CNNs), demonstrating slight accuracy degradations (0.67%–1.34%) compared with the software baseline. A test chip with a 16K 8T SRAM bitcell array is fabricated using a 65-nm process. The measured energy efficiency is 490–15.8 TOPS/W for 1–5 bit ADC resolution using 0.45-/0.8-V core supply. [ABSTRACT FROM AUTHOR]

This study compared three groups (consumers, restaurant managers, and inspectors) in their understanding of restaurant inspection violations under different inspection formats. Addition of a coding word such as critical or non-critical changed interpretation of the seriousness of a violation statement, particularly for restaurant managers and consumers. In addition, seriousness attached to certain words, such as "priority" was not consistent among the three groups. Changes in perception with the use of coding words were similar for consumers and restaurant managers, but inspectors perceived violations differently for the inspection format using the scoring of priority, priority foundation, or core violations. [ABSTRACT FROM AUTHOR]

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively. [ABSTRACT FROM AUTHOR]

We tested the hypothesis that, due to greater hepatic free fatty acid (FFA) load, portal delivery of FFAs, as in visceral obesity, induces hyperinsulinemia and increases endogenous glucose production to a greater extent than peripheral FFA delivery. For 5 h, 10 [micro]eq*[kg.sup.-1]*[min.sup.-] portal oleate (n = 6), equidose peripheral oleate (n = 5), or saline (n = 6) were given intravenously to conscious dogs infused with a combination of portal and peripheral insulin to enable calculation of hepatic insulin clearance during a pancreatic euglycemic clamp. Peripheral FFAs were similar with both oleate treatments and were threefold greater than in controls. Portal FFAs were 1.5-to 2-fold greater with portal than with peripheral oleate. Peripheral insulin concentrations were greatest with portal oleate, intermediate with peripheral oleate (P < 0.001 vs. portal oleate or controls), and lowest in controls, consistent with corresponding reductions in plasma insulin clearance and hepatic insulin clearance. Although endogenous glucose production did not differ between the two routes of oleate delivery, total glucose output (endogenous glucose production plus glucose cycling) was greater with portal than with peripheral oleate (P < 0.001) despite the higher insulin levels. In conclusion, during euglycemic clamps in dogs, the main effect of short-term elevation in portal FFA is to generate peripheral hyperinsulinemia. This may, in the long term, contribute to the metabolic and cardiovascular risk of visceral obesity. insulin resistance; hepatic glucose production; visceral obesity

Neuromorphic vision sensors (NVS) with the features of small data redundancy and transmission latency are widely implemented in Internet of Things applications. Previous studies have developed various object detection algorithms based on NVS's unique event data format. However, most of these methods are only adaptive for scenarios with stationary backgrounds. Under dynamic background conditions, NVS can also acquire the events of non-target objects due to its mechanism of detecting pixel intensity changes. As a result, the performance of existing detection methods is greatly degraded. To address this shortcoming, we introduce an extra refinement process to the conventional histogram-based (HIST) detection method. For the proposed regions from HIST, we apply a practical decision condition to categorize them as either object-dominant or background-dominant cases. Then, the object-dominant regions undergo a second-time HIST-based region proposal for precise localization, while background-dominant regions employ an upper outline determination strategy for target object identification. Finally, the refined results are tracked using a simplified Kalman filter approach. Evaluated in an outdoor drone surveillance with an event camera, the proposed scheme demonstrates superior performance in both intersection over union and F1 score metrics compared to other methods. [ABSTRACT FROM AUTHOR]

This brief proposes a sequence-dependent SRAM-based PUF with enhanced reliability. It expands the CPRs by order of (rows $^{(sequence\,\,length\,\,}{}^{+}{}^{\,\,}{}^{2}{}^{)}\,\, \mathbf {\mathrm {\times }}$ columns) for reliable authentication. The proposed bitcell utilizes split word-lines to control two access transistors separately. The PUF mode turns on two left word-lines and two right word-lines simultaneously, including 18 transistors for generating one-bit data. This proposed technique supports rendering multiple data maps from one chip. Besides, various temperature and voltage combinations can create a reliability map for each data map. A test chip was fabricated in 40 nm CMOS technology. The measured worst bit error rate is 0.8% at the nominal point (1V, $20 \mathbf {\mathrm {^\circ }}$ C). From a single chip, the proposed PUF achieved the hamming distances of 41.29% for one sequence with different orders and 44.93% for other sequences, respectively. The measured inter-chip hamming distance is 49.64%. [ABSTRACT FROM AUTHOR]

Recent progress in fluorescence imaging allows neuroscientists to observe the dynamics of thousands of individual neurons, identified genetically or by their connectivity, across multiple brain areas and for extended durations in awake behaving mammals. We discuss advances in fluorescent indicators of neural activity, viral and genetic methods to express these indicators, chronic animal preparations for long-term imaging studies, and microscopes to monitor and manipulate the activity of large neural ensembles. Ca2+ imaging studies of neural activity can track brain area interactions and distributed information processing at cellular resolution. Across smaller spatial scales, high-speed voltage imaging reveals the distinctive spiking patterns and coding properties of targeted neuron types. Collectively, these innovations will propel studies of brain function and dovetail with ongoing neuroscience initiatives to identify new neuron types and develop widely applicable, non-human primate models. The optical toolkit's growing sophistication also suggests that "brain observatory" facilities would be useful open resources for future brain-imaging studies. Fluorescence tools are lighting up neuroscience and extending our ability to monitor and manipulate the activity of collections of neurons. Kim & Schnitzer guide non-specialists through the explosion of tools for optically monitoring large-scale neural activity, from genetically encoded sensors to microscopes. [ABSTRACT FROM AUTHOR]

This work proposes an static random access memory (SRAM) with column-based split cell-VSS (CS-CVSS), data-aware write-assist (DAWA), and enhanced read sensing margin in 28-nm FDSOI technology. The proposed CS-CVSS and DAWA techniques improve both half-selected (HS) static noise margin (SNM) and write margin. They also improve HS dynamic noise margin (HS-DNM) by leveraging write through virtual ground with reduced load in the proposed write port. The proposed 3T read port enhances sensing margin by minimizing read bitline leakage through negative gate-to-source voltage regardless of cell data. A 16-kb 9T SRAM test chip demonstrated the minimum operating voltage for write and read operations as 0.47 and 0.25 V, respectively. The minimum energy of 6.72 pJ is achieved at 0.5 V. [ABSTRACT FROM AUTHOR]

This article (Colonnade) presents a fully digital bit-serial compute-in-memory (CIM) macro. The digital CIM macro is designed for processing neural networks with reconfigurable 1–16 bit input and weight precisions based on bit-serial computing architecture and a novel all-digital bitcell structure. A column of bitcells forms a column MAC and used for computing a multiply-and-accumulate (MAC) operation. The column MACs placed in a row work as a single neuron and computes a dot-product, which is an essential building block of neural network accelerators. Several key features differentiate the proposed Colonnade architecture from the existing analog and digital implementations. First, its full-digital circuit implementation is free from process variation, noise susceptibility, and data-conversion overhead that are prevalent in prior analog CIM macros. A bitwise MAC operation in a bitcell is performed in the digital domain using a custom-designed XNOR gate and a full-adder. Second, the proposed CIM macro is fully reconfigurable in both weight and input precision from 1 to 16 bit. So far, most of the analog macros were used for processing quantized neural networks with very low input/weight precisions, mainly due to a memory density issue. Recent digital accelerators have implemented reconfigurable precisions, but they are inferior in energy efficiency due to significant off-chip memory access. We present a regular digital bitcell array that is readily reconfigured to a 1–16 bit weight-stationary bit-serial CIM macro. The macro computes parallel dot-product operations between the weights stored in memory and inputs that are serialized from LSB to MSB. Finally, the bit-serial computing scheme significantly reduces the area overhead while sacrificing latency due to bit-by-bit operation cycles. Based on the benefits of digital CIM, reconfigurability, and bit-serial computing architecture, the Colonnade can achieve both high performance and energy efficiency (i.e., both benefits of prior analog and digital accelerators) for processing neural networks. A test-chip with $128 \times 128$ SRAM-based bitcells for digital bit-serial computing is implemented using 65-nm technology and tested with 1–16 bit weight/input precisions. The measured energy efficiency is 117.3 TOPS/W at 1 bit and 2.06 TOPS/W at 16 bit. [ABSTRACT FROM AUTHOR]

This paper presents a novel Capacitance to Digital Converter (CDC) for ultra-low power microphone-based auscultation. The proposed CDC utilizes a continuous-time Capacitance to Voltage Converter (CVC) inside a delta-sigma (ΔΣ) modulator to perform the Delta operation. The multi-bit feedback in the embedded CVC with a capacitive DAC reduces the voltage swing at its output, which permits a larger capacitive signal gain and relaxes the noise requirements. The multi-bit feedback also allows a larger signal swing at the CVC output, and improves the dynamic range. The proposed CDC was fabricated in 0.18 μm CMOS technology and was measured with a commercial capacitive sensor. Measurement results demonstrate that the proposed CDC consumes only 6.3 nJ while achieving 13-bit resolution. This corresponds to a FoM of 0.84 pJ/conversion-step. [ABSTRACT FROM AUTHOR]

We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates < 0.1mW toggling power where the secure data protection is less critical. When compared against the reported counterpart with toggling clock of 50% duty cycle, our proposed data-toggling SRAM (with ~ 3% duty cycle clock divider) occupies ~ 31% smaller IC area and dissipates ~ 29% lower toggling power, resulting in an overall reduction of ~ 51% area × power product. [ABSTRACT FROM AUTHOR]

Objectives: The objective of this retrospective observational study was to determine the incidence of direct‐acting oral anti‐coagulant (DOA) use in patients receiving invasive dental procedures. The secondary objective was to investigate the precautionary measures implemented and the post/intraoperative complications associated with DOA use. Methods: Electronic record database, Axium, was retrospectively reviewed, and patients using NGOA and treated between 2010 and 2017 were identified. Charts of patients who underwent invasive dental procedures were further reviewed to investigate the preoperative/intraoperative precautionary measures taken and identify any intraoperative/postoperative complications. Results: A total of 130 patients were identified, with their annual number steadily rising from 12 in 2011 to 52 in 2016. Among those, 64 patients (49.23%) underwent invasive dental procedures. Pretreatment medical consults were obtained in all patients undergoing invasive procedures; however, only 7 (10.94%) were instructed to discontinue their DOA. Preoperative laboratory testing was obtained for two patients. Intraoperatively, 34 (53.13%) cases of excessive bleeding were reported, all were locally controlled with hemostatic agents. Only 4 instances of postoperative complications were documented. Conclusions: Despite the rise in the use of DOA, there is no consistent pattern for preoperative laboratory testing and DOA discontinuations. Expert consensus may be of great importance to develop practice guidelines. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory dot-product for neural networks. The proposed architecture allows the NVM operations in both 2T2R and conventional 1T1R configurations. The proposed LiM full adder (LiM-FA) improves the delay, the static power, and the dynamic power by $3.2\times $ , $1.2\times $ , and $1.6\times $ , respectively, compared with state-of-the-art LiM-FAs. Furthermore, based on different optimization techniques and robustness analysis, a lower precharge voltage is set for each mode. This reduces the TCAM search energy and 1T1R ReRAM access energy by $1.6\times $ and $1.14\times $ , respectively, compared with the case without optimizations. [ABSTRACT FROM AUTHOR]

The papers in this special section were presented at ISCAS 2021. [ABSTRACT FROM AUTHOR]

This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data through bit-wise comparison, which leads to a larger number of “0s”. To utilize this, a data-aware bitline pre-charge scheme is proposed to minimize the write power for “0”. In addition, a PVT-tracking bias generator compensates for the read bitline leakage to improve the sensing margin. A 32Kb SRAM in 65nm CMOS technology shows successful operation down to 0.36 V with the power of 0.37 μW and the maximum frequency of 0.25 MHz. The minimum energy is 0.3 pJ/access at 0.5 V. [ABSTRACT FROM AUTHOR]

Objective: Photoacoustics has been evolving rapidly in the recent several decades. With the aim of clinical translation, a photoacoustic imaging platform with a portable system size, a miniaturized imaging probe, and convenient handheld capability is of great demand. Methods: In this work, by adopting an ultrathin central-holed matrix array and a compact coaxial photoacoustic design, a water-free handheld photoacoustic imager is developed (weight: 44 g). Optical Monte Carlo simulation and acoustic k-wave simulation are performed to confirm a relatively homogenous photoacoustic sensitivity distribution within a wide field of view (larger than 10 × 10 × 10 mm3). Results: Imaging resolution characterized by imaging two hairs is estimated to be about 0.80 mm in the lateral direction and 0.73 mm in the axial direction. To demonstrate the handheld capability in real time, handheld imaging guided needle biopsy in the rat's abdomen is performed at a rate of about 10 Hz (CNR ∼ 14.3 dB). Furthermore, handheld imaging is also demonstrated on visualizing vasculature (mainly cephalic vein) in the human arm (CNR > 4.1 dB). Conclusion: Results demonstrate that the volumetric photoacoustic imaging system using a central-holed 2D matrix array is an attractive choice for achieving convenient handheld operation in real time. Significance: Such a compact handheld design may promote the clinical translation of photoacoustic technique. [ABSTRACT FROM AUTHOR]

Gesture recognition has increasingly become one of the most popular human–machine interaction techniques for smart devices. Existing gesture recognition systems suffer from either excessive power consumption or large size, limiting their applications for ultralow-power wearable devices. This article presents an accurate area-efficient and low-power real-time gesture recognition system for smart wearable devices. The proposed work utilizes an accurate peak-based gesture classification engine with less memory and a low-resolution and low-power on-chip image sensor for achieving high area efficiency and low power. In addition, the feature extraction architecture removes fixed-pattern noises from the low-power on-chip image sensor for accuracy improvement and employs parallelism for recognition speed enhancement. Thus, the proposed system accomplishes accurate real-time gesture recognition for eight motion hand gestures with an average recognition accuracy of 90.6% and latency of 4.228 ms. Measurement results of a test chip fabricated in 65-nm CMOS demonstrate that the proposed system consumes $137.0~\mu \text{W}$ at 30 frames/s while occupying only 1.78 mm2, which achieves the lowest power and smallest area among the recently reported gesture recognition systems. [ABSTRACT FROM AUTHOR]

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by $25\times $ and $8\times $ lesser for the fluence of $9.82\times 10^{11}$ particles/cm2 and $49.1\times 10^{11}$ particles/cm2, respectively. [ABSTRACT FROM AUTHOR]

This article presents an 8T static random access memory (SRAM) macro with vertical read wordline (RWL) and selective dual split power (SDSP) lines techniques. The proposed vertical RWL reduces dynamic energy consumption during read operation by charging and discharging only selected read bitlines (RBLs). The data-aware SDSP technique combined with vertical write bitlines enhances both the write margin (WM) and the static noise margin (SNM). A 16-kb SRAM test chip fabricated in 65-nm CMOS technology demonstrates the minimum energy consumption of 0.506 pJ at 0.4 V and the minimum operating voltage of 0.26 V. [ABSTRACT FROM AUTHOR]