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Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is using a time-domain delta–sigma $(\Delta\Sigma)$ modulator. This type of TDC with \Delta\Sigma$ modulator can achieve higher resolution by increasing the oversampling ratio, with the advantages of low area and low power consumption. To increase the accuracy by producing true temperature-independent time delay, an external reference clock is utilized, instead of temperature-independent inverter cells, for robust operations. The measured temperature sensors demonstrated a minimum power consumption of 480 nW and a resolution under 0.1 °C. The 3\sigma$ error of the sensor is ±0.99 °C over −20 °C–80 °C temperature range from ten-sample measurement results. The chip area is 0.089 mm2 using a Dongbu 0.18- CMOS process. The conversion rate is 1.25 samples/s. [ABSTRACT FROM PUBLISHER]

A 13.5-mW 10-Gb/s four-level pulse-amplitude modulation (4-PAM) serial link transmitter is presented. To improve the power efficiency, a voltage-mode 4-PAM driver is proposed. It consists of voltage-scaled pull-up and pull-down networks, instead of conventional current switching networks. Not employing a tail current source, the proposed 4-PAM driver achieves the higher output voltage swing and lower power dissipation than conventional 4-PAM drivers. As a result, the proposed 4-PAM transmitter implemented in a 0.13- \mu\m CMOS process achieved 10-Gb/s data rate with only 13.5-mW power dissipation. [ABSTRACT FROM AUTHOR]

A nonlinear behavioural model of power amplifiers is proposed with an improved modelling method to fit up to the alternate channels where the noise contributions are dominant. From a memory polynomial model incorporating memory effects (Ku and Kenney 2003), noise contributions are considered for a better modelling. The proposed modelling method is utilised to model power amplifiers for Wideband Code Division Multiple Access (WCDMA) 1700 and 2100 bands. The power amplifier behaviour is modelled within 1 dB accuracy up to the alternate channels. [ABSTRACT FROM AUTHOR]

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value fromMIN,MAXand the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18 µm CMOS process. The AFC time decreased from 40 to 0.4 µs employing the proposed scheme such that the total lock time is 40 µs with the loop bandwidth of 40 kHz. [ABSTRACT FROM PUBLISHER]