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This study investigated the impact of the post-deposition annealing (PDA) process on the material and electrical properties of copper oxide (Cu2O) and nickel oxide (NiO) thin films deposited on a silicon carbide (SiC) substrate. Through radiofrequency (RF) sputtering, these films were subjected to PDA in a nitrogen (N2) and oxygen (O2) gas environment. Remarkably, the Cu2O films resisted phase transition following the N2 PDA process but exhibited a transition to cupric oxide (CuO) after undergoing the O2 PDA process. The symmetry of Cu 2p in the as-deposited Cu2O film was excellent; however, the phase-transformed CuO films exhibited an increase in binding energy and the emergence of satellite peaks. The Ni 2p exhibited various defects, such as nickel vacancies (VNi) and interstitial oxygen (Oi), in response to the different PDA atmospheres. The rectification ratios of the N2-annealed Cu2O and NiO devices were determined as 1.50 × 107 and 4.01 × 106, respectively, signifying a substantial enhancement by a factor of approximately 789 for the Cu2O/SiC device and 124 for the NiO/SiC device relative to their non-annealed counterparts. The findings of this study indicate that meticulous control of deposition for potential p-type materials such as Cu2O and NiO can significantly improve the performance in applications involving high-throughput and low-cost electronics. [ABSTRACT FROM AUTHOR]

The simulations and experiments for two 400 W low‐speed direct‐drive permanent magnet synchronous generators (PMSGs) installed in a Floating Kuroshio Turbine (FKT) were implemented. The towing tank experiments were carried out at National Taiwan University. A generator can start to harvest current energy at the rotation speed of 30 rpm (corresponding to the current flow rate of 0.36 m/s), and produce the rated power of 400 W at 150 rpm. The speed is very low compared with the published reports. The energy conversion efficiency of the FKT is up to 0.85. The results show that the generated direct current (DC) power is more than 800 W at a flow rate of 1.5 m/s. The power coefficient for the FKT is about 0.4. The energy loss at each stage and the power difference between the testing platform and the towing tank experiment were also analyzed. Moreover, the shape of the FKT is a new design. Compared with other structures, the proposed FKT can easily follow the direction of the ocean current and the depth of the FKT can be adjustable; when it doesn't operate, it will float on the surface so that it is easy for maintenance. [ABSTRACT FROM AUTHOR]

The objective of this paper is to propose a new method to detect the rise of equivalent series resistor in order to realize the online failure prediction of the electrolytic capacitor for LC filter of switching-mode power converter. Characteristics of electrolytic capacitors are introduced in this paper. Different experimental measurements are conducted and shown to illustrate the properties of electrolytic capacitors. The proposed online failure prediction method has the merits of low cost and circuit simplicity. It can be integrated within the package of the electrolytic capacitor to improve its reliability. Hardware experimental results are shown to verify the performance of the proposed method. Index Terms--Electrolytic capacitor, equivalent series resistor, failure prediction, switching-mode power converter.

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V. [ABSTRACT FROM AUTHOR]

Herein, solution‐processed indium gallium zinc oxide (IGZO) thin‐film transistor (TFT) is fabricated utilizing metal nitrates as precursors, and the impact of nitrate ions in different solvents on the performances of IGZO TFT is demonstrated. During IGZO film fabrication, the nitrogen in nitrate species actually dopes into the film in the fashion of different chemical states depending on different solvents. When IGZO precursors dissolve in deionized water (DIW), due to the high polarity of the solvent, metal nitrates are completely dissociated, leading to the conversion of nitrates to nitrides in IGZO film. This nitrogen decreases the density of the interface trap states, thus improving the characteristics of the IGZO TFT. In contrast, when using 2‐methoxyethanol (2‐ME) as the solvent, nitrogen mainly forms nitrogen oxide and acts as a trap density that leads to the degradation of the device performances. By increasing the annealing temperature of IGZO film, nitrogen oxide can convert to metal nitride, resulting in enhanced device performance. The IGZO TFT fabricated using DIW as a solvent with 300 °C annealing temperature exhibits the saturation mobility of 2.5 cm2 V−1 s−1 and Ion/off ratio of >106.5. Herein, a step is made toward the solvent effect on the performance of solution‐processed oxide TFT. [ABSTRACT FROM AUTHOR]

In this letter, a novel edge termination named deep junction termination for silicon superjunction (SJ) MOSFETs is proposed, simulated, and experimentally demonstrated for the first time. By utilizing a typical implantation-and-epitaxy process to form P- and N-pillars for SJ, it is possible to form deep junctions as the device termination with a large radius of curvature and lateral and vertical doping gradation. The 2-D simulation shows that more than 700-V blocking voltage (BV) can be achieved by a 57- \mu \textm drift layer with this novel termination, and experimentally BV as high as 660 V is demonstrated by the fabricated device. [ABSTRACT FROM AUTHOR]

A novel diagonal square array junction barrier Schottky (JBS) diode is created to enhance the forward current and reverse breakdown voltage by increasing the Schottky contact area and shortening the diagonal spacing between two adjacent p+ islands in the active area of a JBS diode. The shape of the p+ islands is square and the positional arrangement of the p+ islands is a diagonal array. Half of the upper and lower p+ islands with smaller areas are connected with the innermost p+ guard ring to create more Schottky contact area and laterally extend the electric field to the edge termination. Results show that the forward current density and reverse breakdown voltage for the diagonal square array JBS diode are 4.2% and 10.7% higher than those for the conventional square array JBS diode, respectively. As the spacing increases, the breakdown voltage for the diagonal square array JBS diode and the conventional square array JBS diode decrease by 3.5% and 7.3%, respectively, indicating that the diagonal square array JBS has more uniform depletion regions and electric field to retain the breakdown voltage. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30- \mu m thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11\,\times \,10^{\mathrm {12}} /cm ^{2} to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19\times 10^\mathrm 12 /cm ^2 to the positive surface charges, both superior to other JTE structures investigated in this paper. [ABSTRACT FROM AUTHOR]

The correlation between barrier inhomogeneities of 4H-SiC Schottky barrier diodes (SBDs) and surface defects and traps for SBDs fabricated with and without chemical–mechanical polishing (CMP) is investigated. 60% of the barrier inhomogeneities of SBDs with invisible surface defects are eliminated when CMP is applied in the refabrication. About 40% of SBDs with carrots inside the active areas exhibit double barriers without using CMP. This excludes that carrots are a cause of barrier inhomogeneities. However, none of the barrier inhomogeneities of the SBDs with carrots can be eliminated by using CMP. Most barrier inhomogeneities of SBDs with various surface defects inside the active areas can be improved by CMP. The difference between the high and low barrier heights of an SBD with CMP was reduced to about 0.02–0.06 eV. Therefore, the leakage current induced by barrier inhomogeneities is also reduced by CMP. Moreover, SBDs with a resistive termination extension (RTE) have a higher barrier height than SBDs without RTE, and there is no direct evidence to show that the inclusion of RTE can induce barrier inhomogeneities. [ABSTRACT FROM AUTHOR]

Design and fabrication of 4H–SiC lateral high-voltage devices on semi-insulating substrates based on the charge compensation principle have been investigated in this work. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, the breakdown voltage (BV) of a single-zone reduced-surface-field (RESURF) device with a 100- \mu\m drift region can be improved from 3360 to 5880 V. The BV can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in BV by 10% charge imbalance variation is also improved from 49% for a single-zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. A 4H–SiC JFET with a two-zone RESURF region was fabricated to demonstrate the advantages of lateral devices based on these concepts. The fabricated lateral 4H–SiC JFET has a BV of 4200 V and a specific on -resistance of 454 \m\Omega\cdot \cm^2. The figure of merit is as high as 38.8 \MW/cm^2. [ABSTRACT FROM AUTHOR]

This research proposes a novel 4H-SiC power device structure—different concentration floating superjunction MOSFET (DC-FSJ MOSFET). Through simulation via Synopsys Technology Computer Aided Design (TCAD) software, compared with the structural and static characteristics of the traditional vertical MOSFET, DC-FSJ MOSFET has a higher breakdown voltage (BV) and lower forward specific on-resistance (Ron,sp). The DC-FSJ MOSFET is formed by multiple epitaxial technology to create a floating P-type structure in the epitaxial layer. Then, a current spreading layer (CSL) is added to reduce the Ron,sp. The floating P-type structure depth, epitaxial layer concentration and thickness are optimized in this research. This structure can not only achieve a breakdown voltage over 3300 V, but also reduce Ron,sp. Under the same conditions, the Baliga Figure of Merit (BFOM) of DC-FSJ MOSFET increases by 27% compared with the traditional vertical MOSFET. Ron,sp is 25% less than that of the traditional vertical MOSFET. [ABSTRACT FROM AUTHOR]

ABSTRACT This article presents a balanced pulse-modulated polar transmitter that is capable of withstanding load mismatch and out-of-band reflection. The balanced architecture directs the reflected power to the isolated port of the 90°-hybrid coupler. Using a rectifier, the reflected power can be recycled and used for assisting the supply of the polar transmitter. A prototype system was implemented and measurement was performed for validation. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1452-1454, 2014 [ABSTRACT FROM AUTHOR]