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Deep neural network (DNN) inference and training produce a large amount of intermediate data. To achieve high energy efficiency, sufficient on-chip buffer is preferred to reduce the energy and time consuming off-chip DRAM access. However, SRAM buffer suffers from large area cost and high standby power due to its large cell size and high leakage current. Although embedded DRAM (eDRAM) offers higher memory density, its energy consumption is high due to frequent refresh operation, which is induced by the short refresh interval (40∼100μs). In this paper, a dual-mode buffer memory based on the CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators. It can operate in both volatile eDRAM mode and non-volatile ferroelectric RAM (FeRAM) mode. The functionality of the proposed dual-mode memory bit-cell design is verified using SPICE simulation with the multi-domain Preisach physical model. A data-lifetime-aware memory mode configuration protocol is proposed to optimize the buffer access energy for both DNN inference and training. Detailed circuitry and architectural support for the dual-mode memory are presented. For DNN training with ferroelectric-field-effect-transistor (FeFET) and SRAM-based compute-in-memory (CIM) accelerator, the proposed dual-mode buffer design improves the overall energy efficiency by 92.2%∼98.7%, 44.1%∼47.6%, 12.6%∼13.0% compared to baseline designs using SRAM buffer with the same buffer area, eDRAM and FeRAM with the same buffer capacity, respectively. For DNN inference with tensor-processing-unit (TPU)-like systolic array, the energy efficiency during computing is improved by 40.7%∼45.6%, 18.4%∼29.6% compared to the designs with eDRAM and FeRAM buffer, respectively. By storing the persistent data using the non-volatile mode, the energy efficiency of systolic array is improved by 2.3×∼5.5× over SRAM-based design when standby is frequent. The chip area overhead of the dual-mode buffer design is 5.2%, 4.1% and 7.2% for FeFET-based-CIM, SRAM-based-CIM and systolic-array-based accelerators using eDRAM buffer, respectively. [ABSTRACT FROM AUTHOR]

The porcine monomyeloid cell line, or 3D4/21 cells, is an effective tool to study the immune characteristics and virus infection mechanism of pigs. Due to the introduction of the neomycin resistance gene and the SV40 large T antigen gene, its genome has undergone essential changes, which are still unknown. Studying the variation in genome structure, especially the large fragments of insertions and deletions (InDels), is one of the proper ways to reveal these issues. In this study, an All-seq method was established by combining Mate-pair and Shotgun sequencing methods, and the detection and verification of large fragments of InDels were performed on 3D4/21 cells. The results showed that there were 844 InDels with a length of more than 1 kb, of which 12 regions were deletions of more than 100 kb in the 3D4/21 cell genome. In addition, compared with porcine primary alveolar macrophages, 82 genes including the CD163 had lost transcription in 3D4/21 cells, and 72 genes gained transcription as well. Further referring to the Hi-C structure, it was found that the fusion of the topologically associated domains (TADs) caused by the deletion may lead to abnormal gene function. The results of this study provide a basis for elaborating the genome structure and functional variation in 3D4/21 cells, provide a method for rapid and convenient detection of large-scale InDels, and provide useful clues for the study of the porcine immune function genome and the molecular mechanism of virus infection. [ABSTRACT FROM AUTHOR]

As AI applications become pervasive on edge device, incrementally learning new tasks is demanded for deep neural network (DNN) models. In this article, we proposed AILC, a compute-in-memory (CIM)-based accelerator for on-chip incremental learning using STT-MRAM technology. On the software side, a network-expansion-based low-precision training algorithm is proposed for incremental learning, where the loss function is modified to handle the unbalanced training dataset. On the hardware side, the detailed CIM accelerator design for incremental learning is illustrated. A workload-aware hardware resources assignment protocol is proposed to improve the throughput when the workload of weight gradient calculation is low. The software simulation results on CIFAR-100 dataset show that the proposed algorithm can effectively support incremental learning despite the device conductance variation exists. System-level benchmark shows that AILC could achieve 147×, 3.7×∼28.7×, 2.05×∼2.9× higher energy efficiency than Nvidia Titan-V GPU, RRAM-based CIM accelerators and edge TPU/GPU, respectively. Compared to the baselines, the throughput of AILC is improved by 2.0×∼2.2× on average with the hardware resources assignment protocol, which results in 4.1×∼21.4× higher throughput than edge TPU/GPU. [ABSTRACT FROM AUTHOR]

Physarum polycephalum, a unicellular and multiheaded slime mould, can form highly efficient networks connecting separated food sources during the process of foraging. These adaptive networks exhibit a unique characteristic in that they are optimized without the control of a central consciousness. Inspired by this phenomenon, we present an efficient exploration and navigation strategy for a swarm of robots, which exploits cooperation and self-organisation to overcome the limited abilities of the individual robots. The task faced by the robots consists in the exploration of an unknown environment in order to find a path between two distant target areas. For the proposed algorithm (EAIPP), we experimentally present robustness tests and obstacle tests conducted to analyse the performance of our algorithm and compare the proposed algorithm with other swarm robot foraging algorithms that also focus on the path formation task. This work has certain significance for the research of swarm robots and Physarum polycephalum. For the research of swarm robotics, our algorithm not only can lead multirobot as a whole to overcome the limitations of very simple individual agents but also can offer better performance in terms of search efficiency and success rate. For the research of Physarum polycephalum, this work is the first one combining swarm robots and Physarum polycephalum. It also reveals the potential of the Physarum polycephalum foraging principle in multirobot systems. [ABSTRACT FROM AUTHOR]

We have experimentally demonstrated robust beta-gallium oxide (β-Ga2O3) ferroelectric (FE) field-effect transistors (FeFETs) on a sapphire substrate operated up to 400 °C. Atomic layer deposited (ALD) Hf0.5 Zr0.5O2 [hafnium zirconium oxide (HZO)] is used as the FE dielectric. The HZO/β-Ga2O3 FeFETs are studied for their synaptic behavior applications at elevated temperatures. The devices show distinguishable polarization switching operation with the output conductance quasi-linearly controlled by the number of input pulses on the FE gate. In a simulation, on-chip learning accuracy reaches 94% at elevated temperatures using the Modified National Institute of Standards and Technology (MNIST) data set with a simple two-layer multilayer perceptron (MLP) network. These ultra wide bandgap semiconductor devices have the potential to fill the need for harsh environment neuromorphic applications. [ABSTRACT FROM AUTHOR]

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN) is demonstrated, with ultratight conductance distribution (<1.5% sigma). First, a two-loop write–verify protocol is proposed. Then, statistical experiments are conducted on RRAM array fabricated in Winbond’s 90-nm process. By incorporating the measured conductance distribution into DNN simulation considering the real weight mapping, inference accuracy with only 0.5% degradation over software baseline is achieved for CIFAR-10 data set even when 128 rows are read-out in parallel. By enabling parallel read-out, the system-level energy efficiency and throughput could be improved by 5.3 × and 4.4 ×, respectively, compared to the 3-bit per cell RRAM used as MLC storage. [ABSTRACT FROM AUTHOR]

Compute-in-memory (CIM) is a promising computing paradigm to accelerate the inference of deep neural network (DNN) algorithms due to its high processing parallelism and energy efficiency. Prior CIM-based DNN accelerators mostly consider full custom design, which assumes that all the weights are stored on-chip. For lightweight smart edge devices, this assumption may not hold. In this article, CIM-based DNN accelerators are designed and benchmarked under different chip area constraints. First, a scheduling strategy and dataflow for DNN inference is investigated when only part of the weights can be stored on-chip. Two weight reload schemes are evaluated: 1) reload partial weights and reuse input/output feature maps and 2) load a batch of input and reuse the partial weights on-chip across the batch. Then, system-level performance benchmark is performed for the inference of ResNet-18 on ImageNet data set. The design tradeoffs with different area constraints, dataflow, and device technologies [static random access memory (SRAM) versus ferroelectric field-effect transistor (FeFET)] are discussed. [ABSTRACT FROM AUTHOR]

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference. [ABSTRACT FROM AUTHOR]

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication. [ABSTRACT FROM AUTHOR]

Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim. [ABSTRACT FROM AUTHOR]

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter–Gummel method is adopted to simulate ion migration with fast convergence achieved. This packet is validated in comparison with the commercial software based on the finite-element method. With its implementation, complete and clear pictures for crosstalk effect in vertically integrated RRAM are captured and compared, where the effects of key physical and geometrical factors are characterized and understood. Some useful suggestions to mitigate its unfavorable influences are given. [ABSTRACT FROM PUBLISHER]

Resistive random access memory (RRAM) is a promising candidate for next generation nonvolatile memory technology. In this paper, electrothermal simulation in 3-D RRAM arrays is performed by using our in-house developed finite difference algorithm, which is validated by comparing the simulated temperature distribution with its counterpart obtained by commercial software. Both crossbar RRAM array and vertical RRAM array are studied comprehensively with careful consideration of the temperature-dependent constitute parameters. Simulations show that the temperature and thermal crosstalk are sensitive to the size and shape of conductive filament, which can further limit the scaling potential of RRAM array through affecting its reliability, such as retention time, current leakage, and so on. Scaling behavior of 3-D RRAM array is studied, and optimization guidance for reducing thermal crosstalk is proposed. The fabrication inaccuracy resulted cell offset has also been examined for investigation of thermal crosstalk. [ABSTRACT FROM PUBLISHER]