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This work focuses on a novel methodology to establish on-wafer calibration standards for the 16-Term Error Calibration Technique. It combines TRL-calibrated data with EM simulation to precisely generate S-parameters of standards. Applied to the advanced BiCMOS 55 nm technology, with a layout maintaining consistent coupling between standards, the 16 error-terms calibration results in significant improvements from 40 GHz onward compared to standard calibration (SOLT or TRL) techniques. Notably, it corrects probe couplings, eliminates discontinuities between frequency bands, and ensures the accuracy of S-parameter measurements. Unlike traditional SOLT and TRL methods, this new approach attributes measured quantities solely to intrinsic transistor behavior.

This paper gives an overall picture from BiCMOS technologies up to THz systems integration, which were developed in the European Research project TARANTO. The European high performance BiCMOS technology platforms are presented, which have special advantages for addressing applications in the submillimeter-wave and THz range. The status of the technology process is reviewed and the integration challenges are examined. A detailed discussion on millimeter-wave characterization and modeling is given with emphasis on harmonic distortion analysis, power and noise figure measurements up to 190 GHz and 325 GHz respectively and S-parameter measurements up to 500 GHz. The results of electrical compact models of active (HBTs) and passive components are presented together with benchmark circuit blocks for model verification. BiCMOS-enabled systems and applications with focus on future wireless communication systems and high-speed optical transmission systems up to resulting net data rates of 1.55 Tbit/s are presented.

This article presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/de-embedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-SPICE co-simulation that integrates the whole calibration cum de-embedding procedure.

This paper presents the first graphene radiofrequency (RF) monolithic integrated balun circuit. It is composed of four integrated graphene field effect transistors (GFETs). This innovative active balun concept takes advantage of the GFET ambipolar behavior. It is realized using an advanced silicon carbide (SiC) based bilayer graphene FET technology having RF performances of about 20 GHz. Balun circuit measurement demonstrates its high frequency capability. An upper limit of 6 GHz has been achieved when considering a phase difference lower than 10° and a magnitude of amplitude imbalance less than 0.5 dB. Hence, this circuit topology shows excellent performance with large broadband performance and a functionality of up to one-third of the transit frequency of the transistor.

This paper presents the characterization of a GFET transistor using a source-pull/load-pull test set. The characterization shows that despite the good fT and fMAX, it is hard to achieve power gain using the GFET device within a circuit configuration. This is due to the very high impedance at the gate making impedance matching at the input extremely difficult. S-parameter characterization is performed and the associated small signal model is developed in order to further analyse and extrapolate the source-pull and load-pull measurement results. A good agreement is observed between small signal model simulation results and source-pull/load-pull measurements. Finally, the model is used to evaluate the optimum power gain of the transistor in a circuit configuration under matched conditions.

This paper deals with SiGe HBTs optimization for power amplifier applications dedicated to wireless communications. In this work, we investigate the fT-BVCEO tradeoff by various collector optimization schemes such as epilayer thickness and dopant concentration, and SIC and CAP characteristics. Furthermore, a new trapezoidal base Germanium (Ge) profile is proposed. Thanks to this profile, precise control of Ge content at the metallurgical emitter-base junction is obtained. Gain stability is obtained for a wide range of temperatures through tuning the emitter-base junction Ge percent. Finally, a comprehensive investigation of Ge introduction into the collector (backside Ge profile) is conducted in order to improve the fT values at high injection levels.