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Datapath synthesis is a crucial step in synthesis flow and aims at globally minimizing an area by identifying shareable logic structures. This paper introduces a novel Directed Acyclic Graph (DAG)-based datapath synthesis method based on graph isomorphism and gate reconfiguration. Unlike algorithms that identify common specification logic, our approach simplifies the problem by focusing on searching for common topology. Leveraging the concept of gate reconfiguration, our algorithm extends the applicability of DAG-based datapath synthesis by transforming a topology-equivalent network into a specification-equivalent network. Experimental results demonstrate up to 23.6% improvement when optimizing the adder–subtractor circuit, a scenario not addressed by existing DAG-based datapath synthesis algorithms. [ABSTRACT FROM AUTHOR]

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget. [ABSTRACT FROM AUTHOR]

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth. [ABSTRACT FROM AUTHOR]

A recent surge of research on deep convolutional neural network (DCNN) has given a challenge on existing computation architecture which has the flows in speed and memory bottleneck. In the pretreatment of deep learning, mask operation is frequently used to remove noise or fetch information. However, under data-intensive conditions, applying mask frequently can put an extremely heavy memory/communication burden on computing system. An efficient substrate of DCNN for ameliorating mask operation is urgently needed. In this paper, we present a self-renewing mask circuit (SRMC) to alleviate/solve earlier problems. First, a new approach to apply mask is presented based on computation-in-memory architecture that implements high-performance processor and high-density memory in the same physical location. Second, we designed the peripheral circuit which can provide self-renewing function to further avoid the data exchange with an external space. As opposed to most other computational element, which calculates two 1-bit data, the proposed SRMC storage multibit value and calculate several of them parallel. The calculating ability of SRMC is significantly superior to those of computational element in general architectures. Moreover, mean filter and edge detector are implemented to illustrate the effectiveness and scalability of the proposed circuit. Finally, we discussed two possible methods to enhance the practicability of our scheme. [ABSTRACT FROM AUTHOR]