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In this article, for the first time, we propose channel characteristic-based deep neural network (DNN) models for accurate eye-height (EH) and eye-width (EW) estimation of high bandwidth memory (HBM) silicon interposer channels. The proposed models preprocess the design parameters that are highly relevant to the characteristics of the HBM channels. By taking account of the contribution of each design parameter to the eye diagram, the proposed models can accurately estimate the EH and EW of the channels even with a limited number of datasets. For verification, the proposed DNN models were applied to the microstrip and stripline channels of an HBM silicon interposer. Only redistributed layer (RDL) was used to clearly see the effect of reflecting the channel characteristics of the proposed method. We compared the proposed DNN models with various regression methods and a conventional fully connected multilayer DNN model. As a result, the proposed DNN models reduced the EH and EW error rates by 22.7 and 43.9% compared to the other regression methods. In addition, the proposed DNN models not only reduced the error rates by 22.0–28.4% but also reduced the computing cost by 8.0–9.4%, compared to the conventional DNN model. Moreover, we compared the proposed models with various DNN models having other preprocessing structures. By showing 26.7 and 28.8% lower EH and EW error rates than the other DNN models, we validated that the proposed models properly consider the most dominant design factors in preprocessing. [ABSTRACT FROM AUTHOR]

Current wireless power transfer (WPT) technology is widely used for various applications because of convenience and safety. However, WPT systems have problems with electromagnetic field (EMF) leakage, which can cause electromagnetic interference (EMI) issues for nearby electrical devices at various frequency ranges. In the case of the Qi standard that operates from 105 to 205 kHz frequency range, the third or fifth harmonic can cause EMI problems for the amplitude modulation bands of a radio corresponding from 530 to 1700 kHz. For the first time, in this article, we propose a frequency-selective EMI reduction method with an additional shielding coil for the effective suppression of EMI radiation of a WPT system. The proposed method reduces the EMI in a specific frequency range and has insignificant effect on the power transfer efficiency (PTE). We experimentally verified that the proposed method with the shielding coil reduced the EMF leakage by 8.96 dB of the third harmonics without reduction of the PTE. Furthermore, we mathematically designed the shielding coil using the proposed method. The mathematical calculation based on the equivalent circuit models is strongly correlated with the experimental measurement results. [ABSTRACT FROM AUTHOR]

In this paper, we first proposed a novel hybrid loop array (HLA) for low leakage electromagnetic field (EMF) level and high efficiency in a wireless high power transfer system. The proposed HLA effectively enhances the system efficiency and shields leakage EMF in a wireless power transfer (WPT) system using kHz range resonant frequency. The key originality of the proposed HLA is the combination of two types of loop coil; shielding loop coil (SLC) and amplifying loop coil (ALC). SLCs reduce leakage EMF, and ALCs significantly enhance the magnetic field from a Tx coil. The simulation and experiment results show that the proposed solution successfully overcomes the limitations of the existing solutions. Analytical modeling and design procedure are introduced and discussed. In addition, the experimental verification of the simulation result is included. We first designed and modeled an HLA considering the coupling effect of neighboring loop coils to evaluate its efficiency and leakage EMF. With the proposed HLA, we demonstrated a 9.36% improvement in the efficiency and 3 dBm reduction in the leakage EMF near the WPT system. [ABSTRACT FROM AUTHOR]

In this paper, we designed and demonstrated a smartwatch strap wireless charging system for the first time. First, we designed a flexible printed circuit board (PCB) coil, shielding material, and receiver (Rx) circuit in a watchstrap. In the design process, we proposed a model for the flexible PCB coil with a bending radius of 40 mm and shielding materials. We used a flexible PCB coil that has 215  μm thickness with dimensions of 54.5 × 16 mm. In addition, ferrite core and sheet are applied on the transmitter (Tx) and Rx coils. We verified the proposed model through a three-dimensional (3-D) electromagnetic (EM) simulation and measurement in the frequency and time domains. The proposed flexible PCB coil inductance modeling results showed 7.5% and 3.4% errors when compared to the 3-D EM simulation and measurement results, respectively. Furthermore, we demonstrated the smartwatch strap wireless charging system using an LG Watch Urbane. A resonance frequency of 100 kHz with the series–series tuning topology is used in accordance with the Qi specifications. Finally, we achieved 30% dc–dc power transfer efficiency and exposed magnetic field of 270 mG, 1 cm away from the system through measurements. [ABSTRACT FROM AUTHOR]

In this paper, we first propose and demonstrate a novel on-interposer active power distribution network (PDN) scheme to efficiently suppress simultaneous switching noise (SSN) in a 2.5-D/3-D integrated circuit (IC). The on-interposer active PDN can change the PDN impedance by controlling on-interposer decoupling capacitors. The SSN in a 2.5-D/3-D IC is suppressed by optimal control of the on-interposer active PDN scheme. The active interposer is a silicon interposer including active circuits in its silicon substrate to enhance the electrical performance of the 2.5-D/3-D IC. A test interposer of the proposed on-interposer active PDN is fabricated with a 0.18- $\mu \text{m}$ CMOS process and assembled on a printed circuit board for measurement and analysis. The active circuits of the proposed scheme and hierarchical PDN are modeled with a distributed RLGC-lumped model for fast simulation. The modeling of the proposed scheme is experimentally verified in the frequency and time domains. We successfully demonstrate that an optimum on-interposer decoupling capacitance for the minimized SSN peak-to-peak voltage was obtained by using the proposed scheme. The proposed scheme efficiently suppressed the SSN in 2.5-D/3-D IC by preventing the SSN generation at antiresonance of the hierarchical PDN. In addition, the proposed scheme is compared with a conventional passive PDN scheme, and the maximum ratio of SSN suppression against the conventional scheme was 17.2%. [ABSTRACT FROM AUTHOR]

In this paper, we, for the first time, designed and analyzed differential high-speed serial links of the silicon interposer including differential through-silicon-via (TSV) channels for a high-bandwidth memory (HBM) graphic module. The meshed ground plane and various parameters were considered in designing the silicon interposer. In addition, superior designs were proposed to improve signal integrity (SI) for the differential channels in the redistribution layer, TSVs, and the meshed ground. SI of the silicon interposer was successfully analyzed, and the corresponding results were verified based on a full 3-D electromagnetic solver and circuit simulations. A number of RLGC parameters were extracted and calculated, then adopted to verify the simulation results. The simulation results for the differential characteristic impedance and insertion loss were compared with those of the equivalent circuit. A mixed-mode conversion matrix was utilized to analyze differential-mode transmission. Moreover, a model for differential TSV channels was proposed to precisely analyze the electrical characteristics. The eye-diagram simulation was conducted to evaluate SI of the proposed designs in terms of an eye-opening voltage and timing jitter. The eye-opening voltage of the proposed design was 0.594 V, which is 45.69% of a peak-to-peak voltage of the assumed peripheral component interconnect (PCI)-express 4.0 interfaces. It is expected that the analysis and design methodologies of differential high-speed serial links for a silicon interposer could be widely adopted in the semiconductor industry. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s. [ABSTRACT FROM AUTHOR]

In this paper, we first propose a modeling method of arbitrary-shaped multilayer printed circuit board (PCB) ground planes and chassis of smartphones in the audio frequency range (20 Hz–20 kHz). The model is proposed to quickly and accurately analyze audio frequency ground voltage noise at an audio circuit that is induced from a time-division multiple access (TDMA) RF power amplifier (PA) while it is switching at an audio frequency during a call. Conventional 3-D electromagnetic (EM) simulation consumes enormous computation time and resources. However, the proposed method models the ground network as a resistive ground distribution network based on the finite-difference method and saves the computation time and resources. We verified the proposed modeling method by comparing ground noise coupling levels obtained from the proposed model, 3-D EM simulation, and measurement in the time and audio frequency domains. The proposed model showed 3.4% and 22.8% differences in the time domain and 3.8% and 14.8% differences at the 217-Hz fundamental frequency in the frequency domain, respectively, compared to 3-D EM simulation and measurement. Furthermore, we used the proposed model to analyze the ground noise coupling between audio circuits and TDMA RF PAs integrated on various designs of PCBs. To verify the correlation between the analysis and the actual performance degradation of audio circuits, we fabricated the PCBs, mounted commercial audio Delta–Sigma modulators and RF PAs, and measured the output of the modulators. The correlation is verified from the modulator on the PCB with the least ground noise coupling showing a spurious-free dynamic range 40.5 dB higher than the modulator on the PCB with the largest ground noise coupling. [ABSTRACT FROM PUBLISHER]

In this paper, we first propose and demonstrate an interposer-level wireless power transfer (WPT) scheme to reduce the number of wired power supply interconnections for high-density silicon interposer-based 2.5-D and 3-D integrated circuits (2.5-D and 3-D ICs). We first suggest the concept of an active silicon interposer, fabricate it with active circuits for WPT, and finally proved its WPT operation. The active circuits are the rectifier and dc–dc converter designed with 0.18- \mu \textm SK-Hynix CMOS process to convert wirelessly delivered ac power from a printed circuit board (PCB) package into dc power. We improved the power transfer efficiency by applying magnetic field resonance coupling with proper coil structure selection. The equivalent circuit model of the WPT interconnection scheme is suggested with analytic equations. For experimental demonstration, the fabricated active silicon interposer is attached on PCB package. The average dc output voltage of the designed CMOS rectifier with an MIM smoothing capacitor was measured 2.21 V, and that of the designed dc–dc converter was measured 1 V, which is a suitable voltage level for 1 V devices in 2.5-D and 3-D ICs. [ABSTRACT FROM PUBLISHER]