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We have developed and simulated a high electron mobility transistor (HEMT) operating in the 5 nm regime. This HEMT uses hafnium oxide (HfO2), a high-k dielectric material, to create an undoped region (UR) beneath the gate. While the gate and undoped regions share equal thickness, the channel length differs. This innovative undoped under the gate dielectric HEMT design mitigates the maximum electric field (V) within the channel area, leading to a significant increase in drain current. The utilization of a high-k dielectric in the HEMT structure results in a saturated Ion current that is 60% higher compared to conventional structures. Specifically, we use an AlGaN/GaN/SiC-based HEMT with an intrinsic section below the gate, using HfO2 as the high-k dielectric substantial, for applications requiring high power and high-frequency power amplifiers. Compare this advanced HEMT design to conventional HEMTs and you will see improved conductivity, a greater drain current (Id), a 54% increase in transconductance (Gm), and a lower on-resistance (Ron). Additionally, advancements in the electric field in the Y direction are seen. This HEMT structure exhibits superior performance compared to alternative materials analyzed. The integration of AlGaN/GaN materials in HEMTs opens up extensive opportunities in the realms of radio frequency very large-scale integration (VLSI) and power electronics. [ABSTRACT FROM AUTHOR]

One promising approach for creating the chip-level connection of multiprocessing system on chip (MPSoC) is asynchronous logic. However, asynchronous systems are susceptible to errors. In this manuscript, the efficient fault-tolerant (FT) quasi-delay-insensitive (QDI) pipeline modules are designed using a delay-insensitive redundant check (DIRC) coding mechanism. The DIRC coding approach can tolerate single and multi-bit transient faults (TFs) in QDI-pipeline modules. The 4-phase 1-of-n coding approach incorporates DIRC-based QDI pipeline stages to strengthen the asynchronous links against TFs. The DIRC-based QDI pipeline stages are further used as asynchronous links in asynchronous network-on-chip ((NoC) for fault-free communication. The performance metrics like chip area, delay, and power parameters are evaluated in detail against different data widths for both basic unprotected and DIRC-based QDI pipeline modules. The DIRC-based QDI-pipeline module with 1-of-4 code uses only <2% chip area with a delay of 7.4 ns and power of 117 mW on Artix-7 chip for data width 128. The code rate of the proposed work decreased by 33.33% for both 1-of-2 and 1-of-4 codes in DIRC-based QDI-pipeline modules. [ABSTRACT FROM AUTHOR]

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several advantages over clock-based synchronous network-onchips (NoCs). The asynchronous router uses a virtual channel (VC) as a primary flow-control mechanism however, the spatial division multiplexing (SDM) based mechanism performs better over input traffics over VC. This manuscript uses an asynchronous spatial division multiplexing (ASDM) based router for NoC architecture on a field-programmable gate array (FPGA) platform. The ASDM router is configurable to different bandwidths and VCs. The ASDM router mainly contains input-output (I/O) buffers, a switching allocator, and a crossbar unit. The 4-phase 1-of-4 dual-rail protocol is used to construct the I/O buffers. The performance of the ASDM router is analyzed in terms of lower urinary tract symptoms (LUTs) (chip area), delay, latency, and throughput parameters. The work is implemented using Verilog-HDL with Xilinx ISE 14.7 on artix-7 FPGA. The ASDM router achieves < 1% chip area and obtains 0.8 ns of latency with a throughput of 800 Mfps. The proposed router is compared with existing asynchronous approaches with improved latency and throughput metrics. [ABSTRACT FROM AUTHOR]