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This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications. [ABSTRACT FROM AUTHOR]

This paper proposes a circuit model of a cross-coupled CMOS AC–DC charge pump (XC–CP) operating in the subthreshold region. The aim is to improve the efficiency of designing XC–CPs with a variety of specifications, e.g., input and output voltages and AC input frequency. First, it is shown that the output resistance (Ro) of XC–CP is much higher than those of CPs with single diodes (SD–CP) and ultra-low-power diodes (ULPD–CP) as charge transfer switches (CTSs). Second, the reason behind the above feature of XC–CP, identified by a simple model, is that the gate-to-source voltages of CTS MOSFETs are independent of the output voltage of the CP. Third, the high but finite Ro of XC–CP is explainable with a more accurate model that includes the dependence of the saturation current of MOSFETs operating in the subthreshold region on the drain-to-source voltage, which is a function of the output voltage of CP. The model is in good agreement with measured and simulated results of XC–, SD–, and ULPD–CPs fabricated in a 250 nm CMOS. [ABSTRACT FROM AUTHOR]

This paper proposes a concept of battery-assisted battery charger with maximum power point tracking for DC energy transducer such as thermoelectric generator and photo voltaic generator, and shows experimental results to prove the concept. The DC energy transducer is connected in series with a battery to increase the voltage. The plus terminal for the DC energy transducer is connected with the input terminal of a DC-DC buck converter, whereas the battery is connected with the output terminal of the converter. Thus, the current is boosted from the input to the output. When the net current to the battery is positive, the system works as a battery charger. To extract the as much power from the DC energy transducer as possible for high charging efficiency, maximum power point tracking is introduced. The converter was designed in 180 nm 3V CMOS with a silicon area of 1.05 mm2. The concept was experimentally proven by varying the reference voltages to control the input voltage. An all-solid-state battery was charged up from 2.2 V to 2.3 V in two hours by the converter with a flexible thermoelectric generator which had an open-circuit voltage of 0.6 V. [ABSTRACT FROM AUTHOR]

This paper pursued both the lower operating power limit and small area of on-chip rectifiers for microwave wireless power transfer (MWPT). RF–DC charge pump rectifiers can operate in the fast switching limit at a high frequency of 920 MHz even with a small stage capacitor Cin of 100 fF, which contributes to an area reduction in the on-chip rectifiers. Circuit design starts with Cin determined as small as possible, followed by the determination of switching transistors and the number of stages. Even at an extremely low input power of 1 μW, wiring resistance in RF inputs is critical. Routing of the RF inputs is designed in line with stage capacitors. Bonding pad structure also affects the lower input power limit. Ground-shielded pad design can reduce the lower limit. Various types of RF–DC charge pump rectifiers are fabricated in 65 nm CMOS. An ultra-low-power diode RF–DC charge pump rectifier with 32 stages had a lower input power limit of −31.7 dBm at an output voltage of 1.0 V. Its small silicon area of 0.011 mm2 allows RF–DC rectifiers to be integrated in sensor ICs. More advanced technology providing MIM capacitors with higher capacitance density and placing switching MOSFETs under the MIM capacitors will further reduce the area of RF–DC charge pump rectifiers, allowing them to be integrated in sensor ICs. [ABSTRACT FROM AUTHOR]

This paper proposes a one-dimensional (1D) maximum power point tracking (MPPT) design which only requires measurement of one parameter (the input voltage of a switched-capacitor charge pump) for calibrating a power converter including the charge pump and thermoelectric generator. The frequency of the clock to drive the charge pump is designed to minimize the circuit area of the entire charge pump circuit for generating a target output current at a specific output voltage. The ratio of the capacitance value of each boosting capacitor (C) to the size of the switching MOSFET can be determined to maximize the transferring current at the same time. When a thermoelectric generator (TEG) is given, its output impedance is determined. Its open-circuit voltage varies with the temperature difference between two plates of the TEG. MPPT maximizes the output power of the charge pump even when the temperature difference varies. It was indicated that the number of stages of charge pump (N) needs to increase when the temperature difference lowers, whereas C needs to decrease inversely proportional to N, meaning that the C–N product should be kept unchanged for MPPT. Demonstration of the circuit design was conducted in 65 nm CMOS, and the measured results validated the concept of the 1D MPPT. [ABSTRACT FROM AUTHOR]

This paper discusses a relationship between thermoelectric generator (TEG) electrical parameters, power efficiency of converters, and power consumption of loads in autonomous sensor modules. Based on the method discussed, one can determine the total number of TEG units together with the number of TEG arrays and the number of TEG units connected in series per array when the characteristics of TEG unit, the minimum temperature difference in operation, the power conversion efficiency of the converter and the load condition are given. A practical design flow to minimize TEG cost is proposed and demonstrated, taking the maximum open circuit voltage of TEG and the dependence of the power conversion efficiency of the converter on the input voltage of the converter into consideration. The entire system including TEG and a Dickson charge pump converter, which were designed through the proposed flow, was validated with SPICE. [ABSTRACT FROM AUTHOR]

This paper discusses a design methodology to efficiently determine the best combination of rectenna (rectifier and antenna) to minimize the input power under a given output condition for microwave wireless power transfer (MWPT) without any other external components, such as a matching network, for cost reduction. A linearized equivalent circuit model is expanded upon to include the microstrip line connecting the antenna and rectifier. Based on the model, the design flow is presented that has mainly three steps: (1) Determination of the equivalent rectifier input impedance and the amplitude of input voltage by running SPICE simulation, (2) Drawing contour plots of input power by rectifier candidate on the antenna impedance plane by conducting model calculation and impedance loci of antenna candidates on the contour plots, and (3) Selecting the combination of antenna and rectifier which gives the minimum input power for all the combinations. To validate the equivalent circuit model and design flow, a single-diode (SD) rectifier and a voltage-doubler (VD) rectifier were fabricated in 65 nm CMOS. The input power to generate 100 μA at 1 Vdc was measured and compared. The model, SPICE and measurement are in good agreement with each other that VD has 30–50% lower input power than SD does. In addition, the sensitivity of the parasitic elements, such as the microstrip line and the bonding wires and pads on the input power, are investigated to explore the design space for rectenna. [ABSTRACT FROM AUTHOR]

In this paper, we show that an additional inductor–capacitor–inductor filter can increase the oscillation amplitude of the enhanced swing Colpitts oscillator (ESCO), and call this topology the more enhanced swing Colpitts oscillator (mESCO). When it is connected with a rectifier, the DC–DC boost conversion ratio can be increased, especially for low-voltage sensor ICs or energy harvesting. This paper focuses on the electrical characteristics of mESCO. The oscillation frequency was modeled as a function of the circuit parameters of mESCO. The common gate voltage gain (ACG), defined by the ratio of the drain voltage amplitude to the source voltage amplitude of the switching MOSFET of mESCO, was also modeled under the assumption that all the circuit elements are ideal. The model was validated with a SPICE simulation. For ACG < 1.5, the model was in good agreement with the SPICE results within 10%. In addition, the drain voltage amplitude vda was modeled by assuming that the average transconductance of the MOSFET in a half cycle is null when the long-channel Shockley model is used. vda needs to be sufficiently high to have a large DC–DC boost conversion ratio. The model can predict the tendency that vda increases as ACG approaches unity. We found that the voltage difference of the drain voltage amplitude to the source voltage amplitude is a constant even when the circuit parameters, and thereby ACG are varied. [ABSTRACT FROM AUTHOR]

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit. [ABSTRACT FROM AUTHOR]

In this brief a brief tutorial of charge pump topologies for management of self-powered nodes in ultra-low-power applications, such as Internet of Things nodes, is presented. It aims to provide to the designer guidelines to choose the most suitable solution, according to the given design specifications. After a brief historic evolution, the main design equations of charge pumps and a collection of the recent proposed topologies and regulation schemes are discussed, allowing for qualitative insight into the state-of-the-art of integrated topologies. [ABSTRACT FROM AUTHOR]

Summary: This paper introduces a design strategy to reduce rise time of charge pumps maintaining equal the silicon area, which is effective when the load capacitance is lower than the total charge pump capacitance. The strategy relies on an unconventional pumping capacitors sizing, which set them not equal and follows a linear distribution. The approach is based on a theoretical analysis and is validated through post‐layout simulations using a 130‐nm complementary metal‐oxide semiconductor (CMOS) standard technology. The simulations demonstrate the advantages of the proposed design strategy and the accuracy of the theory. [ABSTRACT FROM AUTHOR]

This brief shows that the output impedance of Dickson charge pumps with an arbitrary number of stages defined by the total power loss in the switching devices and the output voltage is identical to the previous result calculated by the output current and voltage. A relationship between the output current and power efficiency is also given in a simple form. [ABSTRACT FROM AUTHOR]

This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be ϵ N\bf MIN, where \varepsilon is 1.5–1.7 and N\bf MIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage. [ABSTRACT FROM AUTHOR]

This brief proposes an explicit Dickson charge pump model, including the effect of the resistance of switching devices on the pump performance. Using this model, one can estimate an optimum clock frequency and the size of the transferring transistors in terms of the main pump capacitors, the auxiliary capacitors, and the transfer transistors to maximize the output current under the same silicon area in a given technology. [ABSTRACT FROM PUBLISHER]

We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during nand flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm nand cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler–Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm nand cells. [ABSTRACT FROM AUTHOR]

The article discusses the design methodology for multiple charge pump circuits in large scale integrations (LSIs) where there is no negligible power and ground line resistance. It presents a proposed behavior model for a charge pump that includes input parameters such as local power and ground voltages. It is stated that this will allow the system designer to minimize overall area by identifying the specifications on each pump and power and ground resistance using the behavior model.

Memory chips need large capacitors in their periphery to drive boosted word-lines and bit-lines for read and write operations. In a previous work, scalable capacitors were proposed for 3D crosspoint memory to keep the area for the capacitors constant over technology generations. This paper proposes the capacitance models of three types of wiring capacitors: (1) vertical capacitor, (2) vertical and horizontal capacitor with next-neighbor wires connected with the other terminal, and (3) vertical and horizontal capacitor with next-neighbor pairs connected with the other terminal. These models are based on Wong's crossover capacitor model to determine the capacitor structure with the highest capacitance density in 3D crosspoint memory technology. One can determine the best structure through optimizing the process parameters such as the height H of the insulation material between the metal wires and the thickness T of the metal wires and the design rules such as the width W and space S of metal wires. The model accuracy was in good agreement with the measurement of twelve types of capacitor structures fabricated in a 180 nm 6 metal standard CMOS process with the maximum error of 20%. Contour plots of the capacitance density across H vs. S where it is assumed that W = T = S are shown. As a result, the boundary condition regarding H and S is determined per 3D crosspoint memory technology with three, four, or five levels of wires. [ABSTRACT FROM AUTHOR]

Reports on the development of a 64–megabit flash memory with flexible block redundancy and fast accurate word-line voltage controller. Introduction of a negative-gate channel-erase NOR flash memory cell technology; Characteristic of the chip; Power supply voltage for flash memories.

Presents two circuit techniques in order to scale high-voltage transistors for high-density negative-gate channel-erasing NOR flash memories. Reduction of the maximum internal voltage by 0.5 V; Capability of the technique to realize both low noise and low ripple voltage; Effect of high coupling cell on high-voltage transistor scaling.

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time. [ABSTRACT FROM AUTHOR]

This paper describes a charge pump system for a flexible thermoelectric generator (TEG). Even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with low- and high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. How the system can be designed is also described in detail. A design demonstration was performed for the TEG with 400 Ω. The fabricated system was also measured with a flexible-type TEG based on carbon nanotubes. Even with an output impedance of 1.4 kΩ, the system converted thermal energy into electric power of 30 μW at 2.5 V to the following sensor ICs. [ABSTRACT FROM AUTHOR]

This paper proposes an AC-DC converter for electrostatic vibration energy harvesting. The converter is composed of a CMOS full bridge rectifier and a CMOS shunt regulator. Even with 1 V CMOS, the open circuit voltage of the energy transducer can be as high as 10 V and beyond. Bandgap reference (BGR) inputs a regulated voltage, which is controlled by the output voltage of the BGR. Built-in power-on reset is introduced, which can minimize the silicon area and power to function normally found upon start-up. The AC-DC converter was fabricated with a 65 nm low-Vt 1 V CMOS with 0.081 mm2. 1 V regulation was measured successfully at 20–70 °C with a power conversion efficiency of 43%. [ABSTRACT FROM AUTHOR]

This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm2 fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits. [ABSTRACT FROM AUTHOR]

This paper shows how clocked AC-DC charge pump circuits can be optimally designed to have the minimum circuit area for small form factor vibration energy harvesting. One can determine an optimum number of stages with simple equations and then determine the capacitance of each pump capacitor to have a target output current at a target output voltage. The equations were verified under a wide range of design parameters by comparing the output current with the simulated one. The output current of the circuit designed by the equations was in good agreement with the simulated result, to within 5% for 98% of the 1600 designs with different parameters. We also propose a design flow to help designers determine the initial design parameters of a clocked AC-DC charge pump circuit (i.e., the number of stages, capacitance per stage, and the total size of rectifying devices) under the condition that the saturation current of a unit of the rectifying device, clock frequency, amplitude of the voltage generated by the energy transducer, target output voltage, and target output current are given. SPICE simulation results validated theoretical results with an error of 3% in terms of the output current when a clocked AC-DC charge pump was designed to output current of 1 μA at 2.5 V from a vibration energy harvester with an AC voltage amplitude of 0.5 V. [ABSTRACT FROM AUTHOR]