Search

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability. [ABSTRACT FROM PUBLISHER]

Abstract: This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. [Copyright &y& Elsevier]

The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location. [ABSTRACT FROM AUTHOR]

The effects of damage on mixed-signal (MS)/radio-frequency (RF) circuits integrated with metal–insulator–metal (MIM) capacitors and advanced metal–oxide–semiconductor field-effect transistors (MOSFETs) are studied in this work. The impact of damage on an MIM oxide is evaluated by connecting its capacitor top metal (CTM) to an upper-level metal with a large antenna ratio (ARCTM) used in an actual CTM circuit connected to an interconnect. In addition to the dielectric degradation of a transistor, we also investigate the damage-enhanced negative bias temperature instability (NBTI) degradation of a transistor with its gate electrode connected to an MIM capacitor with a large ARCTM for various gate oxide thicknesses. A model is proposed to explain the experimentally observed dependence of NBTI degradation on ARCTM and accurately simulate failure distributions in the presence of plasma damage. [ABSTRACT FROM AUTHOR]