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In this letter, a voltage reference circuit based on amorphous InGaZnO-based (a-IGZO) thin-film transistors (TFTs) is reported for the first time. Both enhancement-mode and depletion-mode TFTs in the circuit were fabricated by the use of local hydrogen doping. The 1-V reference voltage ($\text{V}_{\text {REF}}$) was achieved with an operating voltage ranging from 1.2 V to 5 V, where the line sensitivity of $\text{V}_{\text {REF}}$ was 0.9%/V and the quiescent consumption was as low as 90 nW. The proposed voltage reference circuit was able to generate complementary- to-absolute temperature coefficients, resulting in stable temperature characteristics. The temperature coefficient (TC) of $\text{V}_{\text {REF}}$ and $\text{I}_{\text {REF}}$ was studied experimentally, where the TC of $\text{V}_{\text {REF}}$ was 2.3 mV/° at a temperature spanning from 27 ° to 77 °. [ABSTRACT FROM AUTHOR]

In this article, we have comprehensively investigated the electrical properties of split-gate trench (SGT) power MOSFETs under mechanical strains. The static and dynamic electrical properties of SGT power MOSFETs under both uniaxial and biaxial strains are examined thoroughly. It is found that both uniaxial and biaxial compressive strains improve the drain current (${I}_{d}$), while uniaxial and biaxial tensile strains do the opposite. The influence of strain is correlated with drain voltage (${V}_{d}$), and biaxial strains are slightly more effective than uniaxial strains. The mechanical strains do not change the threshold voltage (${V}_{{\mathrm {th}}}$), breakdown voltage (BV), capacitances, and switching characteristics. The piezoresistance coefficients of the SGT power MOSFETs are evaluated. It is also proved that both biaxial and uniaxial compressive strains can effectively decrease the figure-of-merit (FOM) of SGT power MOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage (${V} _{\text {BD}}$) was significantly enhanced, and the ${V} _{\text {BD}}$ of over 60 V is achieved in the TFT with the stair length (${L} _{\text {stair}}$) of $3~\mu \text{m}$. The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs’ ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the ${V} _{\text {BD}}$ of the device. Finally, the exponential trade-off relationship between the ${V} _{\text {BD}}$ and the ON-state resistance (${R} _{\text{ON}}$) was established. [ABSTRACT FROM AUTHOR]

In this paper, a single particle irradiation experiment is performed on the 600 V trench insulated gate bipolar transistor for the first time. The experimental results show that, at the collector voltages of 100 V and 300 V, single event gate rupture occurs in the device under the linear energy transfer of 81.35 MeV cm2/g. The damage occurs in the gate oxide layer near the bottom of the trench gate. The simulation results show that the holes accumulated at the bottom of the trench gate increase the electric field under irradiation, which causes the failure of the gate oxide. Furthermore, the hardening device structure is proposed by increasing the thickness of the bottom gate oxide. [ABSTRACT FROM AUTHOR]

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance (gm), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance (Ron) and improve the BV of the nLDMOSFET, due to the mobility enhancement. [ABSTRACT FROM AUTHOR]

Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is found that there are different degradation mechanisms with different amplitudes of ac gate stress, including the maximum operating gate voltage (Vgmax) stress and the maximum substrate current (Isubmax) stress. For the Vgmax condition, the ON-resistance (RON) decreases first and increases finally, which is attributed to two competitive degradation mechanisms. One is the hot holes injection at the bird’s beak during the gate pulse edges, and the other one is the hot electrons injection nearby the drain during the high state level of gate pulse. However, for the Isubmax stress, the dramatical injection of hot electrons nearby the source-metal edge during the high state level of gate pulse is always the main degradation mechanism, resulting in a monotonous increase of RON. Moreover, the threshold voltage (Vth) degradations could be neglected due to the intact channel region under the Vgmax and Isubmax conditions. In this way, the Isubmax condition is regarded as the worst stress, and an improved device with a linear-doped buried-p-well (BP) structure beneath the P-body has been proposed to restrain the degradation under the worst stress condition. [ABSTRACT FROM AUTHOR]

Compared with the full shallow trench isolation (full-STI) lateral double-diffused MOS (LDMOS), the split-STI LDMOS has been demonstrated as a superior device with better breakdown voltage (BVOFF and specific on-resistance (RON, sp) by virtue of its low resistance current path and dielectric reduced surface field effect. The layout of STI may not only be restricted in one pattern. Instead, it can have a variety of changes based on the split-STI structure. Actually, improvement of RON, sp can be achieved upon modifying the STI layout pattern. In this way, four STI layout patterns, named split-STI, stair-STI, slope-STI, and H-shape-STI, are proposed. However, there is lack of information about the impacts of STI layout patterns on the reliability features of LDMOS. Therefore, in this article, the reliability features of the LDMOS with different STI layout patterns are investigated in detail, including electrical safe operating area (e-SOA), electro-static discharge (ESD) robustness, and hot carrier injection (HCI) degradation. Combining the experiment and technology computer-aided design (TCAD) simulation, the root causes of different reliability features are analyzed and discussed. Comparing them each, the LDMOS with H-shape-STI is recommended because of its better reliability features. [ABSTRACT FROM AUTHOR]

A planar gate U-shaped (PGU) channel silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) featuring divided gates (G1 and G2) is proposed, which aims to suppress the gate voltage (VG) overshoot and improve the di/dt controllability. In the conventional PGU structure, the hole accumulating and the electric potential rising in the JFET region leads to a displacement current to overcharge the gate during the turn-on transient. Two gate connection modes (Mode A and B) for the proposed PGU structure are discussed. Mode A with a grounded G2 can effectively enhance the VG stability, however, degenerating the on-state voltage (VON). Mode B shields the displacement current by a pre-charged G2. G2 is driven with a separate gate resistor to the main gate G1, which results in an improved di/dt controllability without deteriorating VON. When adjusted for the same turn-on loss of 5.28mJ/cm2, the di/dt of the proposed PGU structure with mode B is 74% lower than that of the conventional PGU structure. [ABSTRACT FROM AUTHOR]

In this paper, we report the experimental extraction of ballistic transport parameters of high-performance Germanium Nanowire nMOSFETs (Ge NWTs) with lengths ${L}_{\text {NW}} = {40}$ –100 nm, width ${W}_{\text {NW}} = {40}$ nm, and height ${H}_{\text {NW}} = {10}$ nm using temperature-dependent measurements. The extracted contact resistivity ($\rho {c}$) and sheet resistance (Rsh) imply that parasitic series resistance (${R}_{\text {SD}}$) of fabricated Ge NWTs is affected by $\rho _{c}$ of the metal-nGe (${3.42} \times {10}^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ at 292 K), which decreases with the increase in temperature. Ballistic efficiency (BE) is found to be 22%–47% at 292 K depending on the dimension of the device. It decreases with increased temperature and increases with ${L}_{\text {NW}}$ scaling down to 40 nm. The transition region with fluctuating BE is observed near ${L}_{\text {NW}} = {50}$ –60 nm, where the electron transport enters deeper into bthe allistic regime. BE is found to be sensitive to temperature and drops from 58% (170 K) to 37% (390 K) for ${L}_{\text {NW}} = {40}$ -nm Ge NWT. Therefore, in order to maintain the high ballisticity of the devices, it is important to optimize the device structure and eliminate the self-heating effect. [ABSTRACT FROM AUTHOR]

In this letter, we present an experimental investigation on electrical properties of lateral IGBTs (LIGBTs) under an uniaxial mechanical strain for the first time. Both ON-state and turn-off characteristics of LIGBT under an uniaxial strain are studied extensively. The uniaxial strain is applied both parallel and perpendicular to the channel direction. The uniaxial tensile strain will increase the collector current (${I} _{C}$) and the uniaxial compressive strain will decrease the ${I} _{C}$ , while the breakdown voltage (${V} _{\textit {BD}}$) is not affected. The parallel strain and perpendicular strain affect the ${I} _{C}$ distinctly in both the linear and saturation regions. The piezoresistance coefficient of LIGBT under the parallel strain is more than three times that of nMOSFET in the linear region. The parallel tensile strain declines the ON-state voltage drop (${V} _{ \mathrm{\scriptscriptstyle ON}}$) and increases the turn-off time (${t} _{ \mathrm{\scriptscriptstyle OFF}}$) and turn-off loss (${E} _{ \mathrm{\scriptscriptstyle OFF}}$). While the perpendicular tensile strain decreases the ${V} _{ \mathrm{\scriptscriptstyle ON}}$ , ${t} _{ \mathrm{\scriptscriptstyle OFF}}$ , and ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ simultaneously, which is extremely beneficial for real applications. The mechanisms of these strain effects are studied. [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]

In this paper, we study the low-frequency noise in the Ge nanowire (NW) nMOSFETs with sub-100-nm channel length. The low-frequency noise with 1/ ${f}$ characteristics is proved to origin from the carriers’ mobility fluctuation. The dependences of low-frequency noise on NW geometry, channel length, equivalent oxide thickness (EOT), and channel doping concentration are examined by evaluating the Hooge parameters. It is shown that the low-frequency noise declines when the channel length of Ge NW nMOSFETs scales down, which is attributed to the electrons’ near ballistic transport. The electrons suffer more scatterings in the channels beneath the side walls of NWs or in the highly doped channels. The gate-oxide optimization is strongly demanded with the scaling down of EOT. Ultrascaled Ge NW nMOSFETs promise the enhancement of on-state performance and the suppression of low-frequency noise simultaneously. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively study the carriers’ mobility and the effect of back-gate bias ( V \textsf {bg} ) in Ge-on-insulator (GeOI) MOSFETs with various working modes, including accumulation mode (AM) nMOSFET, inversion mode (IM) nMOSFET, AM pMOSFET, and IM pMOSFET. The results show that the AM nMOSFETs and pMOSFETs have higher drain currents and carriers’ mobility. The electron mobility increases under positive V \textsf {bg} and decreases under negative V \textsf {bg} . While the hole mobility has the opposite V \textsf {bg} dependence. The carriers’ mobility of AM MOSFETs is proved to benefit more from V \textsf {bg} due to the increase of carriers’ densities. The peak mobility enhancements of more than 100% for holes and 35% for electrons are achieved in GeOI MOSFETs by applying V \textsf {bg} . [ABSTRACT FROM PUBLISHER]

We demonstrate an experimental study on the ballistic transport behavior of sub-100 nm GeOI n-MOSFETs, by adopting an ultrafast pulsed I–V system for measurement. High performance GeOI n-MOSFETs suffer severer self-heating effect and traps in the dc characterization process than in a “real” high-speed IC circuit. In this letter, the ballistic transport parameters for nanoscale Ge n-MOSFETs are extracted by the pulsed I–V method, and is compared with the SOI n-MOSFETs. The ballsiticity for Ge MOSFETs is higher than Si transistors at the same gate length L\text {G} . Furthermore, the scalability of the ballistic parameters for Ge n-MOSFETs is modeled and predicted for the sub-10-nm technology nodes. [ABSTRACT FROM PUBLISHER]

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( L\mathrm{ ch} ) from 100 to 40 nm, a NW height ( H\mathrm{ NW} ) of 10 nm, the NW widths ( W\mathrm{ NW} ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( g\max ) as high as 1057~\mu \textS/\mu \textm are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters. [ABSTRACT FROM PUBLISHER]

In this paper, we report, for the first time, that surface roughness scattering is not necessarily the dominant scattering mechanism in the high-normal-field region of Ge nMOSFETs. This statement is quite different from the well-recognized situation in Si MOSFETs. In Ge(100), phonon scattering is dominant in the high-field region. Thus, it is difficult to increase the high-normal-field mobility in Ge(100) nMOSFETs by controlling the interface roughness. In contrast, because Ge(111) and Ge(110) are free of intervalley phonon scattering, the high-field mobility in Ge(111) and Ge(110) nMOSFETs could be enhanced by the Ge interface engineering. Furthermore, different from that in Si nMOSFETs, mobility limited by surface roughness scattering in Ge nMOSFETs shows a strong temperature dependence due to the valley occupancy change of electrons. The results in this paper should facilitate efforts to increase the high-normal-field mobility in Ge nMOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, we experimentally investigated the effects of four types of strains, uniaxial tensile strain, uniaxial compressive strain, biaxial tensile strain, and biaxial compressive strain, on the negative bias temperature instability (NBTI) degradation behaviors of Si pMOSFETs. The strains were applied using a wafer bending system to avoid processing effects on the NBTI characteristics as a result of strain engineering. We confirm experimentally, for the first time, that both uniaxial and biaxial compressive strains are advantageous in terms of the NBTI improvement in Si pMOSFETs. However, the NBTI reliability was degraded under both uniaxial and biaxial tensile strains. These results could not be explained by considering only the gate leakage current change due to the strain. The strain-induced modulation of the interaction between the carriers and Si-H bonds at the interface must also be considered. [ABSTRACT FROM AUTHOR]

Alloy scattering in a sSi/Si0.5Ge0.5/strained Silicon on Insulator (SOI) (sSOI) quantum-well (QW) p-MOSFET is investigated by hole density modulation through applying back-gate biases. The hole mobility under negative back-gate biases is found degraded by intensified alloy scattering at low electrical field because more holes are distributed in the bulk Si0.5Ge0.5. At higher electrical field, the higher density of holes populated at the Si/Si0.5Ge0.5.interface and less holes in the bulk Si0.5Ge0.5.result in less pronounced alloy scattering, leading to mobility enhancement under negative back-gate biases. This confirms experimentally that alloy scattering does not play a significant role in the hole mobility of sSi/Si0.5Ge0.5/sSOI QW p-MOSFETs under normal operating mode. [ABSTRACT FROM PUBLISHER]

To investigate and understand the reliability behavior of strained silicon devices, the changes of gate currents (Ig) and substrate currents (Isub) in n and p-channel metal-oxide-semiconductor field-transistors (MOSFETs) under different types of mechanically applied tensile stresses have been studied. It has been observed that, under the uniaxial tensile stress, both Ig and Isub of pMOSFETs increase with the increase of applied stress under the inversion and the accumulation conditions. However, an opposite stress dependence in nMOSFETs has been observed for Ig and Isub in both the inversion and the accumulation regimes. Similar changes have been found for Ig and Isub of nMOSFETs under biaxial tensile stress. The observations are explained by the strain induced band structure modulation and the repopulation of carriers. [ABSTRACT FROM AUTHOR]

Understanding the p-n junctions is of great importance because p-n junctions are the essential elements of semiconductor devices. In this study, we experimentally investigated the strain induced electrical properties modulation of Si p+-n and n+-p junctions. It is found that, under the uniaxial tensile stress, the current in the large-forward-bias region increases significantly, while a rather small current increase is observed in the diffusion-current-dominant region. Besides, the ideality factors in the diffusion-current-dominant region and the large-forward-bias region decrease when the amount of the applied stress increases. The observations are explained by the strain induced variations in energy band structure, their effect on minority carrier concentrations, and the piezoresistance effect. [ABSTRACT FROM AUTHOR]

The Poisson's ratio of a material characterizes its response to uniaxial strain. Materials normally possess a positive Poisson's ratio - they contract laterally when stretched, and expand laterally when compressed. A negative Poisson's ratio is theoretically permissible but has not, with few exceptions of man-made bulk structures, been experimentally observed in any natural materials. Here, we show that the negative Poisson's ratio exists in the low-dimensional natural material black phosphorus and that our experimental observations are consistent with first-principles simulations. Through applying uniaxial strain along armchair direction, we have succeeded in demonstrating a cross-plane interlayer negative Poisson's ratio on black phosphorus for the first time. Meanwhile, our results support the existence of a cross-plane intralayer negative Poisson's ratio in the constituent phosphorene layers under uniaxial deformation along the zigzag axis, which is in line with a previous theoretical prediction. The phenomenon originates from the puckered structure of its in-plane lattice, together with coupled hinge-like bonding configurations.