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Given numerous nonlinear loads in modern power systems, quantities of current harmonics will seriously pollute the power environment. The three-level active power filter (APF) is an effective method to compensate for harmonics. This paper designs the current loop of three-level APF and investigates the phase-locked loop based on the second-order generalized integrator (SOGI) to improve the harmonic compensation performance. In order to observe the load currents, grid voltages, and currents of the APF system, a three-level APF experiment monitor platform based on ethernet interface software is designed. The ethernet communication board is designed based on the W5300 chip, and the ethernet interface software of the APF system is compiled by Visual Studio. The experimental results show that current harmonics can be effectively compensated by the three-level APF, and the designed ethernet interface software can observe voltage, current, and internal-variable waveforms, which is convenient for experimental debugging and monitoring. [ABSTRACT FROM AUTHOR]

High current qualities and high efficiencies are always two important characteristics for power converters. However, it is challenging to achieve the two targets simultaneously. In this paper, the dead‐time‐effect elimination pulse‐width‐modulation (PWM) for improving current qualities and the discontinuous PWM (DPWM) for reducing switching losses are combined, proposing a double‐modulation‐wave DPWM. An additional modulation wave is added, whose amplitude is adjusted according to the current polarity. By utilizing the added drive pulses in the current freewheeling stage, the proposed double‐modulation‐wave DPWM successfully reduces the dependence on the current polarities. The overmodulation phenomenon brought by the added modulation wave is analysed, which is proved to be negligible for achieving the maximum modulation index of 1.15. Finally, the effectiveness of the proposed double‐modulation‐wave DPWM is experimentally verified at a switching frequency of 40 kHz. [ABSTRACT FROM AUTHOR]

In order to overcome the drawbacks of the conventional passive loads with constant parameters, single-phase AC electronic loads with the back-to-back topology have emerged. However, in low-voltage and low-power situations, the grid voltage will be affected by harmonic currents and easily distorted. Therefore, a variable power-factor control strategy based on the second-order generalized integrator frequency locked loop (SOGI-FLL) is proposed. SOGI-FLL is adopted to improve the phase locking accuracy under the distorted grid voltage, and the fundamental and quadrature components are obtained, based on which a control scheme is designed to continuously adjust power factors; the power factor angles of rectifier side and inverter side are controlled cooperatively to reduce dc-link oscillations. Experimental results show that, the designed single-phase low-voltage AC electronic load can simulate capacitive, resistive and inductive loads, respectively, and the power factor is continuously adjustable in the range of 0.5~1.0. [ABSTRACT FROM AUTHOR]

The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times. [ABSTRACT FROM AUTHOR]

No dead-time is contained in the existing dead-time elimination pulsewidth modulation (PWM) for three-phase three-level T-type converters, where complementary drive pulses are allocated alternatively according to polarities of output currents. Consequently, the dead-time effect can be inherently avoided. However, the dependency on current polarities seriously limits its widespread application. Wrong current polarities, e.g., in a dynamic process, will lead to the output-voltage disappearance, thus aggravating the possible “algebraic loop” issue and impairing the stability of the system. In this article, in order to reduce the dependency on current polarities while retaining the characteristic of dead-time-effect elimination, a double-modulation-wave PWM is proposed by modifying the dead-time elimination PWM. Two modulation waves with a magnitude difference are adopted for generating underlap periods between complementary drive pulses, which can avoid the shoot-through failure and no dead-time effect will be generated. And to further simplify the implementation process, the two modulation waves are decomposed by introducing a magnitude-adjustment factor related to the current polarity. Whereas it is also due to the employment of two modulation waves, extra issues of overmodulation, single drive pulses, and a shorter underlap period may occur, which are analyzed in detail and the negative effect can be avoided. Finally, the proposed PWM is experimentally verified, showing the effectiveness on harmonic suppression and the reduced dependency on current polarities. [ABSTRACT FROM AUTHOR]

Given the high complexity of the conventional three-level space-vector pulsewidth modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced. [ABSTRACT FROM AUTHOR]

The adoption of fast-switching silicon carbide (SiC) devices enables power converters to operate at high switching frequencies (e.g., 100 kHz). However, as a limiting factor at high switching frequencies, the dead-time in the conventional pulsewidth modulation (PWM) can cause significant voltage losses, bring serious low-frequency voltage/current harmonics, and reduce the linear modulation region with lower dc-link voltage utilization. Using the dead-time compensation can effectively eliminate the dead-time effect but further reduce the linear modulation region. The dead-time elimination PWM essentially has no dead-time effect. But due to the abandon of drive pulses for generating synchronous rectification, it has a lower converter efficiency, as well as current jumps at zero-crossings. In this article, to overcome the drawbacks of the conventional PWM and the dead-time elimination PWM, a double-modulation-wave PWM for dead-time-effect elimination and synchronous rectification is therefore proposed, where extra drive pulses for generating synchronous rectification are added based on the dead-time elimination PWM. The added drive pulses can also help with mitigating current jumps at zero-crossings. At last, the proposed PWM is experimentally validated and compared with the conventional PWM and the dead-time elimination PWM at 100 kHz on a three-phase converter with SiC mosfets and SiC Schottky diodes, showing the merits of low voltage losses, low output harmonics, high dc-link voltage utilization, large linear modulation region, and high efficiency. [ABSTRACT FROM AUTHOR]

In a three-phase three-level grid-connected inverter, the ac output current ripple actually fluctuates four times per switching period with each fluctuation generating some core loss. However, only the two larger fluctuations are considered in most loss estimation methods, resulting in a smaller core loss evaluation. In this letter, an alternative method has, hence, been proposed, beginning with the deduction of fundamental and ripple equivalent circuits from the inverter. These circuits permit current ripple to be calculated, from which its four fluctuations are all considered for forming the dual current-ripple envelopes (DCREs). These DCREs, together with the fundamental current and a selected core loss model, can then be solved to give the estimated fundamental and ripple core loss values. The nonlinear characteristic of the filter inductor has also been considered in the calculation of the DCREs and the core loss. The estimated values have eventually been verified through testing with a 10-kW three-phase T-type three-level grid-connected inverter. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]

The adoption of silicon carbide (SiC) MOSFETs and SiC Schottky diodes in power converters promises a further improvement of the attainable power density and system efficiency, while it is restricted by several issues caused by the ultrafast switching, such as phase-leg shoot-through (“crosstalk” effect), high turn-on losses, electromagnetic interference (EMI), etc. This paper presents a split output converter, which can overcome the limitations of the standard two-level voltage source converters when employing the fast-switching SiC devices. A mathematical model of the split output converter has been proposed to reveal how the split inductors can mitigate the crosstalk effect caused by the high switching speed. The improved switching performance (e.g., lower turn-on losses) and EMI benefit have been demonstrated experimentally. The current freewheeling problem, the current pulses and voltage spikes of the split inductors, and the disappeared synchronous rectification are explained in detail both experimentally and analytically. The results show that the split output converter can have lower power device losses compared with the standard two-level converter at high switching frequencies. However, the extra losses in the split inductors may impair the efficiency of the split output converter, which is verified by experiments in the continuous operating mode. A 95.91% efficiency has been achieved by the split output converter at the switching frequency of 100 kHz with suppressed crosstalk, lower turn-on losses, and reduced EMI. [ABSTRACT FROM AUTHOR]

When faced with distorted grid voltage, more harmonics will appear in the output currents of the grid-connected inverters. The grid-voltage feedforward strategy, as the most direct solution to compensate the harmonics, however, is seriously affected by the errors in the grid-voltage feedforward loop, such as delays. This issue is more significant for high-power inverters, where the switching frequency is relatively low (< 5 kHz), and the grid-interface inductance is small (< 0.5 mH). The errors mainly include the signal distortion caused by the conditioning circuits, the control delay of the digital controller, and the zero-order hold (ZOH) characteristic of pulse width modulation (PWM). In this paper, several improvements have been made to reduce the signal distortion and compensate the delays. A second-order Butterworth low-pass filter in the conditioning circuit is carefully designed with the maximum flat magnitude response and the almost linear phase response to avoid distorting the measured grid voltage. Furthermore, based on the conventional repetitive predictor, an open-loop simplified repetitive predictor is proposed to compensate the delays in the grid-voltage feedforward loop. Three predictive steps are achieved by the open-loop simplified repetitive predictor to compensate the delays: one step for the delay caused by the conditioning circuit, the second step for the control delay of the digital controller, and the third step for the ZOH characteristic of PWM. The effectiveness of the improved grid-voltage feedforward strategy are experimentally validated on a 250-kVA solar power generation system, where the current harmonics are effectively attenuated. In addition, the inverter starting current is suppressed. [ABSTRACT FROM AUTHOR]

Presents corrections to author information in the above named paper. [ABSTRACT FROM AUTHOR]