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In this paper, a novel design-for-manufacture-aware detailed routing algorithm that seeks to minimize the thickness range of the chip surface after copper damascene process is proposed. The paper is based on an electroplating (ECP) and chemical mechanical polishing (CMP) model and predictors for final thickness range are abstracted. The proposed detailed routing is implemented in a W-shape multilevel full-chip routing framework using depth first search and branch-and-bound techniques in maze backtracking. Experimental results show that compared to maze routing (MR) (that does not consider CMP), the improvements in the average metal density standard and the average amount of dummy fill are 12.0% and 6.99% respectively. Compared to density-driven maze routing (DMR) that considers only CMP but does not consider ECP, the improvements in the average metal density standard and the average amount of dummy fill are 0.53% and 0.72%, respectively. So, the proposed algorithm can obtain improvement in optimizing CMP while the wire length and vias are not increased clearly and the completion rate is guaranteed. Therefore, the yield of chips is improved. [ABSTRACT FROM AUTHOR]

This paper proposes a novel stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering lognormal leakage current variations. The new method, called StoEKS, applies Hermite polynomial chaos to represent the random variables in both power grid networks and input leakage currents. However, different from the existing orthogonal polynomial-based stochastic simulation method, ex- tended Krylov subspace (EKS) method is employed to compute variational responses from the augmented matrices consisting of the coefficients of Hermite polynomials. Our contribution lies in the acceleration of the spectral stochastic method using the EKS method to fast solve the variational circuit equations for the first time. By using the reduction technique, the new method partially mitigates increased circuit-size problem associated with the augmented matrices from the Galerkin-based spectral stochastic method. Experimental results show that the proposed method is about two-order magnitude faster than the existing Hermite PC-based simulation method and many order of magnitudes faster than Monte Carlo methods with marginal errors. StoEKS is scalable for analyzing much larger circuits than the existing Hermit PC-based methods. [ABSTRACT FROM AUTHOR]

The reliability of Power/Ground networks is becoming significantly important in modern integrated circuits, while decap insertion is a main approach to enhance the power grid safety. In this brief, we propose a fast and efficient decap allocation algorithm, and adequately consider the leakage effect of decap. This approach borrows the idea of random walks to perform circuit partitioning and does subsequent decap insertion based on locality property of partitioned area, which avoids solving a large nonlinear programming problem in traditional decap optimization process. The optimization flow also integrates a refined leakage current model for decaps which makes it more practical. Experimental results show that our proposed method can achieve approximate 15X speed up over the optimal budget method within the acceptable error tolerance. Also this algorithm only causes a few penalty area to compensate the leakage effect. [ABSTRACT FROM AUTHOR]

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant via addition. In addition, a rvia-driven maze routing algorithm is also integrated in the system to improve the insertion of redundant vias. Finally a redundant via placement heuristic is adopted to enhance the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing system. Besides much enhancement obtained in the aspect of redundant via placement, the system also obtains high routing completion rate, minimized total wire length and total number of vias in satisfactory runtime. [ABSTRACT FROM AUTHOR]

In this brief, the authors take a first look at the leakage effects of decaps in power/ground (P/G) grid optimization. Through the use of an approximate leakage current model, it is revealed that simple usage of the leakage model in traditional optimization methods cannot help in reducing noises on P/G grids, and it even hurts power consumption due to overadded decaps. Therefore, it is necessary to develop an efficient method to budget decaps when leakage effect is considered. Here, a new two-stage approach to solve this problem is proposed. Experimental results demonstrate the effectiveness of our new method. [ABSTRACT FROM AUTHOR]

This brief deals with the crosstalk minimization problem in an integrated routing resource assignment stage containing several operations between global routing and detailed routing. A two-step heuristic algorithm consisting of coarse assignment and detailed assignment is proposed. In coarse assignment, shield lines are planned based on the chromatic number of a light coarse coupling graph, and the assignment of segments that are longer than a predefined threshold is solved with semidefinite programming. In detailed assignment, a strategy based on a dynamic priority queue is introduced to mitigate common problems caused by sequential routing. Experimental results on a set of benchmarks show significant reduction in coupling length between sensitive segments compared to a prevalent bipartite-matching-based algorithm. [ABSTRACT FROM AUTHOR]

Floorplanning is a critical phase in physical design of very large-scale integration (VLSI) circuits and has received much attention recently due to the increased importance of hierarchical design and intellectual property (IP) blocks. Many heuristic algorithms were proposed to perturb the floorplan and search for better solutions, e.g., simulated annealing and genetic algorithms. To optimize the floorplan using stochastic optimization algorithm, topological representation is one of the most important and fundamental issues.