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Abstract In this paper, a differentially fed broadband dual‐polarised dipole antenna with parasitic elements is proposed. The presented antenna comprises a pair of strip dipoles as driven elements, four square patches as internal parasitic elements, four rectangular patches with cut corners as external parasitic elements, and two pairs of coaxial cables as feeding structures placed orthogonally to excite the driven strip dipoles to achieve ±45° dual polarisation. Furthermore, two additional dual‐polarisation modes can be simulated and a broadband dual‐polarised antenna can be obtained by positioning the external and internal parasitic elements to the end and at the edge of driven elements, respectively. The presented antenna provides wide bandwidth using these dual‐polarisation modes. The measurement results indicate that the presented antenna has excellent characteristics with a wide impedance bandwidth (IBW) of 68.4% (|Sdd11|

Abstract A magnetic near‐field probe (H‐field probe) with dual output has been developed using a four‐layer printed circuit board (PCB) technique. To achieve the improvement of detection sensitivity, the symmetrical double‐loop is adopted to double the detection signal while suppressing the electric field coupling, which is also illustrated in a circuit model. The calibration factor (defined as the ratio of the external magnetic field to the induced response voltage of the probe) of the proposed H‐field probe reaches 37.74 [dB (A/m)/V] at 0.5 GHz with the loop area of 0.8 mm2, resulting in a better sensitivity than the single‐loop probe. For the suppression of unwanted electric field a floating shield is added to the bottom of the probe, leading to an excellent common electric field suppression ratio of 29 dB in the frequency range up to 10 GHz. The probe is also characterised by parameters such as high differential electric field suppression, spatial resolution and probe influence on the device under test.

AC positive bias temperature instability (PBTI) of germanium nMOSFETs with GeO2/Ge and Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests were conducted on both types of devices, the experiment data shows the inserted DC stress phase has little impact on the following AC stress kinetics on GeO2/Ge nMOSFETs but introduce a significant “additional DC generation” on Si-cap/Ge devices. The “additional DC generation” is ascribed to the existence of energy alternating defects (EAD) according to previous studies. Energy distribution under DC and AC stress further demonstrate that EAD are significant on Si-cap/Ge but negligible on GeO2/Ge devices. Effective lifetime prediction is carried out and compared under DC stress after discharge (with a purposely introduced measurement delay) and AC stress on both GeO2/Ge and Si-cap nMOSFETs. The results show GeO2/Ge nMOSFETs’ effective lifetime exhibits no difference under two stress modes, while Si-cap/Ge nMOSFETs’ effective lifetime is underestimated using DC stress after discharge approximation without considering the EAD-induced “additional DC generation”. An extra 0.14V 10-year Vdd design margin can be obtained for Si-cap/Ge nMOSFETs to gain higher performance by taking “additional DC generation” into account. The conclusion is beneficial for process optimization and PBTI reliability improvement of Ge nMOSFETs.

In this article, a novel broad circularly polarized antenna (CPA) with circular-slot ground is presented. The circular-slot CPA is consisted of a circular-slot ground, an I-shaped slit and a semicircle loop feeding structure. By using semicircle loop feeding structure and adding a slit into the circular-slot ground as perturbation elements, the multiple CP resonant modes could be stimulated simultaneously. To demonstrate to the design radiational, an antenna model was printed, manufactured, and tested. The tested results reveal that the proposed antenna has a broad 3-dB ARBW of |S11|

The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in the increase of low frequency noise (LFN). The trap densities near the silicon/gate oxide interface introduced by stress are extracted using the LFN method. NBTI-induced gate current increase is observed for Core device, but not for I/O device. It is result from the enhanced tunneling process, which is induced by the increase of electric field in the gate oxide after charge trapping at or near the channel interface. The gate width and length dependences of NBTI are observed. The enhanced NBTI degradation observed in short channel and narrow channel device is result from the enhanced NBTI effect at channel edge regions. The larger hole concentration is a main cause of the more serious NBTI degradation at the channel edge regions, including the nearby region of STI sidewall along the channel width direction and the gate edge region along the channel length direction. This conclusion is also verified by the TCAD simulations.

MIS-HEMT is one of the most promising structures to prohibit the unfavorable gate leakage in conventional AlGaN/GaN HEMTs. However, the extra insulator layer introduces massive border traps at insulator/AlGaN interface and results in the poor reliability. In this brief the energy distribution of border traps in AlGaN/GaN MIS-HEMT gate stack is extracted and investigated through a discharging-based trap energy profile technique. The technique adopts spot-Id sense measurement with 1 millisecond measurement time to capture the “whole (both fast and slow)” border traps. The results are beneficial to improve the reliability of AlGaN/GaN MIS-HEMT.

For the MEMS capacitive accelerometer, parasitic capacitance is a serious problem. Its mismatch will deteriorate the performance of accelerometer. Obtaining the mismatch of the parasitic capacitance precisely is helpful for improving the performance of bias and scale. Currently, the method of measuring the mismatch is limited in the direct measuring using the instrument. This traditional method has low accuracy for it would lead in extra parasitic capacitive and have other problems. This paper presents a novel method based on the mechanism of a closed-loop accelerometer. The strongly linear relationship between the output of electric force and the square of pre-load voltage is obtained through theoretical derivation and validated by experiment. Based on this relationship, the mismatch of parasitic capacitance can be obtained precisely through regulating electrostatic stiffness without other equipment. The results can be applied in the design of decreasing the mismatch and electrical adjusting for eliminating the influence of the mismatch.

In this paper, we have presented an atomistic quantum simulation study to investigate the device performances of GaSb/InAs heterojunction tunnel field-effect transistors (TFETs) with nanometer body thicknesses. It is revealed that the thin junction induced quantum confinement effect results in a heterojunction type transition from type-III to type-II as the junction thickness reduces, which can be used as an effective modulation of the TFET device performance. It is found that as the channel thickness decreases, both the ON current and OFF current of the device decrease significantly due to the quantum confinement induced effective band gap enlargement. In addition, the OFF current of the heterojunction GaSb/InAs TFET is always larger than that of the homojunction InAs TFET, which is possibly caused by the GaSb/InAs interfacial state assisted tunneling. It is also revealed that the subthreshold swing of the heterojunction TFET does not change much as the channel thickness is reduced. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the degradation mode and mechanism of AlGaN/GaN based high electron mobility transistors (HEMTs) during high temperature operation (HTO) stress. It demonstrates that there was abrupt degradation mode of drain current during HTO stress. The abrupt degradation is ascribed to the formation of crack under the gate which was the result of the brittle fracture of epilayer based on failure analysis. The origin of the mechanical damage under the gate is further investigated and discussed based on top-down scanning electron microscope, cross section transmission electron microscope and energy dispersive x-ray spectroscopy analysis, and stress simulation. Based on the coupled analysis of the failure physical feature and stress simulation considering the coefficient of thermal expansion (CTE) mismatch in different materials in gate metals/semiconductor system, the mechanical damage under the gate is related to mechanical stress induced by CTE mismatch in Au/Ti/Mo/GaN system and stress concentration caused by the localized structural damage at the drain side of the gate edge. These results indicate that mechanical stress induced by CTE mismatch of materials inside the device plays great important role on the reliability of AlGaN/GaN HEMTs during HTO stress. [ABSTRACT FROM AUTHOR]

Non-filament 3D vertical RRAM (VRRAM) is a promising technology for emerging high-density memory applications. In this Letter, the layer-dependent resistance variability at both low resistance state (LRS) and high resistance state (HRS) is assessed on state-of-the-art 8-layer 3D VRRAMs. 2048 devices are measured with the aid of an FPGA-controlled relay matrix which enables automated switching of devices without changing the cabling. The results show LRS exhibits little layer dependence while both the average and the standard variation of HRS decrease from the top layer to the bottom layer. A qualitative speculation is proposed to explain the observation based on the high-resolution transmission electronic microscope image. This work is beneficial for future 3D VRRAM circuit design and performance improvement. [ABSTRACT FROM AUTHOR]

In this work, the effects of hydrogen on an AlGaN/GaN metal insulator semiconductor field effect transistor (MISFET) with SiNx gate dielectric were investigated. It is found that after hydrogen exposure, (1) the AlGaN/GaN MISFET exhibits better DC performance with larger maximum transconductance, (2) the gate lag phenomenon is effectively suppressed and (3) the 1/f noise performance is improved with lower noise magnitude. These results are different from previous observations in other III–V semiconductor devices. Based on the theoretical analysis by space charge limited current and low-frequency noise models, we propose that the hydrogen treatment induces hydrogen incorporation into SiNx, which could passivate the defect centers. These findings demonstrate the high hydrogen tolerance of AlGaN/GaN MISFETs. [ABSTRACT FROM AUTHOR]

The effects of displacement damage induced by 3 and 6 MeV protons in AlGaN/GaN high-electron-mobility transistors (HEMTs) are investigated. For the 6 MeV protons at a dose of 5 × 1014 cm−2, a 12% decrease in saturation current, a 3.8% decrease in the peak transconductance, a 0.3 V positive shift of the threshold voltage, and a three-to fourfold decrease in reverse gate leakage current are observed compared with the pre-irradiation values. The main degradation mechanism is considered to be the generation of deep trap states in the band gap, which remove electrons and reduce the carrier mobility in a two-dimensional electron gas (2DEG). Both the carrier removal rate and negatively charged trap density can be extracted, which shows that about 3500 proton injections lead to one carrier removal. Proton fluence and energy are found to be two key parameters that affect the degradation characteristics of irradiated GaN HEMTs. [ABSTRACT FROM AUTHOR]