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To address these issues, recent works employ hardware-aware neural architecture search (HW-NAS) to automatically find the best architecture with the highest accuracy while reducing memory and computations costs to meet the limitations of the edge devices at hand [[26]]. Combining the generation of hardware accelerators with the creation and training process of a neural network model opens up the possibility of a co-optimizing compiler for the hardware and software components of the neural network architecture that could maximize the efficiency of the generated platform. Keywords: Edge-AI; machine learning; hardware acceleration; co-design; auto-ml; maschinelles Lernen; Hardware-Beschleuniger; Co-Design; AutoML EN Edge-AI machine learning hardware acceleration co-design auto-ml DE maschinelles Lernen Hardware-Beschleuniger Co-Design AutoML 767 776 10 09/06/22 20220901 NES 220901 1 Introduction - AI for edge devices Recent achievements in artificial intelligence, particularly machine learning with deep neural networks, are enabling the implementation of a wide range of applications. 4 Training pipelines for Edge-AI Storage space and power consumption limitations may not be only addressed on hardware level, but can already be considered when either training or adapting (and retraining) a neural network model for the use on commodity-of-the-shelf resource-constrained general purpose hardware. [Extracted from the article]