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In current critical area models, it is generally assumed that the defect outlines to be circular and the conductors to be rectangle or merge of rectangles. However, real extra defects and conductors associated with optimal layout design exhibit a great variety of shapes. Based on mathematical morphology, a new critical area computational method is presented, which can be used to estimate critical area of short circuit in semiconductor manufacturing. The results of experiment on the 4*4 shift memory layout show that the new method predicts the critical areas practicably. These results suggest that proposed method could provide a new approach for the yield perdition. [ABSTRACT FROM AUTHOR]