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This paper proposed a low-power H.264 deblocking filter algorithm. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. By exploiting this feature, whole deblocking filter or its some parts can be deactivated during execution, and its power consumption can be significantly reduced up to 20.3%. A low-power H.264 deblocking filter architecture was also proposed. Simple control circuit can totally or partially deactivate deblocking filter, and common hardware performs both horizontal and vertical filtering. The proposed low-power deblocking filter was implemented in silicon chip using 0.35 μm standard cell technology. The gate count is about 20,000 gates. The maximum operation frequency is 108 MHz. The maximum throughput is 30 frame/s with CCIR601 image format. [ABSTRACT FROM AUTHOR]

Recently, the progress of information and communication technologies leads to web-based education. However, one of these problems is that it is very difficult to find out proper educational materials over the billions of unclassified and unrelated web materials. Well-designed directory services and classification systems of educational materials in the Internet are indispensable for effective web-based education. In this paper, we propose novel directory services and classification systems for effective Korean language learning. We analyzed the elementary components of Korean language learning, and exploit them to develop effective directory services and classification systems. We also propose a guideline to develop them. We also consider peer-to-peer networking service as searching and exchanging educational material. [ABSTRACT FROM AUTHOR]

This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there are quite a large number of non-coded blocks. When the number of the non-coded blocks in a frame is known at the start of frame decoding, the workload of the video decoding can be estimated. Consequently, the supply voltage of VLSI circuits can be lowered, and the power consumption can be reduced. In the proposed scheme, the encoder counts the number of non-coded blocks and stores this information in the frame header of the bitstream. Simulation results show that the proposed scheme reduces the power consumption to about 1/20. [ABSTRACT FROM AUTHOR]