101 results on '"Malik, Sharad"'
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2. Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking
3. Synthesizing Environment Invariants for Modular Hardware Verification
4. ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions
5. Post-Silicon Fault Localization with Satisfiability Solvers
6. Propositional SAT Solving
7. Lazy Self-composition for Security Verification
8. Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions
9. IC3 - Flipping the E in ICE
10. Trace-based Analysis of Memory Corruption Malware Attacks
11. Fast Interpolating BMC
12. Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom
13. Reduction of Resolution Refutations and Interpolants via Subsumption
14. Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation
15. SAT Based Verification of Network Data Planes
16. Model Checking Unbounded Concurrent Lists
17. Modeling Firmware as Service Functions and Its Application to Test Generation
18. Runtime Verification: A Computer Architecture Perspective
19. Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search
20. passert: A Tool for Debugging Parallel Programs
21. Verification of Computer Switching Networks: An Overview
22. Parallel Assertions for Architectures with Weak Memory Models
23. Wolverine: Battling Bugs with Interpolants
24. Parameterized Model Checking of Fine Grained Concurrency
25. Boolean Satisfiability
26. MADL—An ADL Based on a Formal and Flexible Concurrency Model
27. Architecture Description Languages for Retargetable Compilation
28. A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors
29. A Case for Runtime Validation of Hardware
30. On Solving the Partial MAX-SAT Problem
31. Solving Quantified Boolean Formulas with Circuit Observability Don’t Cares
32. Lemma Learning in SMT on Linear Constraints
33. Symmetry Reduction in SAT-Based Model Checking
34. Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems
35. Zchaff2004: An Efficient SAT Solver
36. Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms
37. Power Analysis of Embedded Software: First Step Towards Software Power Minimization
38. Architecture Description Languages for Retargetable Compilation
39. Retargetable Very Long InstructionWord Compiler Framework for Digital Signal Processors
40. Performance Estimation of Embedded Software with Instruction Cache Modeling
41. The Quest for Efficient Boolean Satisfiability Solvers
42. Challenges in Code Generation for Embedded Processors
43. Power Analysis of Embedded Software: A First Step Towards Software Power Minimization Manuscript received June 15, 1994; revised August 23, 1994. The work of V. Tiwari was supported by an IBM Graduate Fellowship. The work of S. Malik was supported by an IBM Faculty Development Award. IEEE Log Number 9406371
44. A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library
45. Sat and ATPG: Algorithms for Boolean Decision Problems
46. Design Tools for Application Specific Embedded Processors
47. Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation
48. Embedded Software Implementation Tools for Fully Programmable Application Specific Systems
49. Optimal Live Range Merge for Address Register Allocation in Embedded Programs
50. Program Path Analysis
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