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Cryptographic coprocessors are inherent part of modern Systemon- Chips. It serves dual purpose - efficient execution of cryptographic kernels and supporting protocols for preventing IP-piracy. Flexibility in such coprocessors is required to provide protection against emerging cryptanalytic schemes and to support different cryptographic functions like encryption and authentication. In this context, a novel crypto-coprocessor, named CoARX, supporting multiple cryptographic algorithms based on Addition (A), Rotation (R) and eXclusive-or (X) operations is proposed. CoARX supports diverse ARX-based cryptographic primitives. We show that compared to dedicated hardware implementations and general-purpose microprocessors, it offers excellent performance-flexibility trade-off including adaptability to resist generic cryptanalysis. [ABSTRACT FROM AUTHOR]

Erlang programming language is developed for programming concurrent, distributed and fault-tolerant systems. The native support for concurrency makes Erlang an efficient language for multi-core and even many-core programming. The support for large number of light-weight processes in distributed computing environment makes Erlang a good choice for cloud computing. Building more cores on a single chip is a trend in processor design. Intel Xeon Phi coprocessor , which is equipped with at least 60 cores, is the first commercial many-core product released by Intel. Xeon Phi coprocessor is encapsulated in a PCIe card and communicates with host operating system through a specialized interface library called SCIF. This paper introduces the architecture of Xeon Phi coprocessor and analyses the internals of SCIF programming interface first. Then this paper proposes a solution that integrates the computing power of multi-core host machine and Xeon Phi many-core coprocessor transparently. The solutions implements a high efficient SCIF-based Erlang distribution carrier as a plugin into Erlang virtual machine, and extends Erlang VM itself to support remote port access in order to support process location policy defined in this solution. In the end, this paper shows a practical use case of the proposed solution in cloud service environment: improve web server capacity without modifying user program. The performance evaluation shows that the capacity of a web server is improved at least 4 times. [ABSTRACT FROM PUBLISHER]

On the wave of technology scaling, digital designers are quickly approaching the limits of current technologies. At the same time, deep submicron architectures are becoming more prone to transient errors and permanent faults. Swarm intelligence represents an interesting source of inspiration already used in the past for the design of decentralized-control hardware architectures with intrinsic properties of scalability, adaptability and fault tolerance, with a configuration-free approach. This paper presents the first swarm coprocessor for floating point array processing with native multitasking support. The coprocessor, designed around a nature-inspired processing fabric, has been integrated on a Virtex6 FPGA with a MicroBlaze host processor and preliminarily evaluated on common applications. The performance of the system, joined to its fault tolerance support, reveals the potentialities of the approach opening to architectural improvements and mapping of safety-critical digital signal processing applications. [ABSTRACT FROM PUBLISHER]

In the transition of applications from the traditional enterprise infrastructures to cloud infrastructures, scalable database management system plays an important role in efficiently managing and analysing unprecedented massive amount of data. Compared to RDBMSs, NoSQL databases, are more attractive in addressing this challenge. However, it is not easy to manage data in NoSQL database effectively for non-expert users because of the rare data-organization support. A poor data organization may accidentally abuse the features of NoSQL database and achieve unsatisfactory performance. Therefore, a systematic method for NoSQL database data-schema design is a timely and important problem for researchers and practitioners. HBase, as a particular NoSQL database offering, relies (a) on HDFS, for its distributed and replicated storage, and (b) on coprocessors, for efficient parallel query processing. To harness the potential parallelism benefits, an appropriate partitioning of the data across the HBase storage is required. we investigate the effectiveness of the three-dimensional data model, which uses the “version” dimension of HBase to store the values of a data item over time. We have experimented and evaluated the performance impact of this type of data model with two data sets, of different sizes and different time lengths. For each of these data sets, we have compared the performance of several ad-hoc queries, implemented with HBase Coprocessors framework, across different data schemas, some of which (do not) use the third HBase dimension. The experiment results demonstrate improved performance with the data schemas that use the third dimension of HBase. [ABSTRACT FROM PUBLISHER]

This paper presents a compact hardware architecture for long integer multiplication and proposes a strategy to increase the computational efficiency of the Karatsuba algorithm on FPGA. The presented architecture aims to provide an efficient and compact architecture to be used where long integer multiplication is definitely required such as Cryptography, especially Public Key Cryptography (PKC), Coding theory, DSP and many more. There are several studies in the literature related to increase the efficiency of multiplication, especially in public key cryptography. From our point of view, the main advantage of this method over other existing methods is that recursive utilization of hardware resources with tight scheduling brings better performance with smaller logic area. Our coprocessor is also suitable for multiplications of polynomials in GF(p) and GF(2k). Our method achieves highest available frequency of FPGA. We compare our hardware performance figures for different bit width multiplication with other reported studies. The results show that our architecture combines performance with small area size. [ABSTRACT FROM PUBLISHER]

Host intrusion detection systems operating on the host under observation itself are limited by an adversary's ability to subvert all data collection and the detection and mitigation mechanisms themselves. Although coprocessor architectures have been proposed to avoid this security mechanism integrity problem, they either involve the application of non-standard hardware or rely on host-bound application programming interfaces (API). This is why, so far, they are only used in the field of network intrusion detection. In this paper, we present our results concerning a concurrent host memory sampling mechanism based on direct memory access (DMA) and demonstrate that it is possible to de-couple GPU kernel execution, thereby providing temporary isolation from the host and allowing data sampling actions to be taken without interruption. We present a security analysis of our approach and detail a proof-of-concept implementation of the autonomous concurrent monitoring and sampling system, thus, validating that self-sufficient data sampling using a commodity coprocessor (i.e. a GPU) is indeed possible. [ABSTRACT FROM PUBLISHER]

The design and implementation of complex embedded systems including custom hardware and software is still to a large degree based on a collaboration of semi-manual and often poorly interconnected design methods and tools. This usually results in repetitive and longer development cycles. This paper describes an intelligent method to automate and accelerate the hardware generation process. Indeed, a VHDL parser is developed to provide an automated path from VHDL entry to Coprocessor design. To prove the correctness of our method, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application show that the proposed framework can rapidly and easily generate coprocessor. It leads to the design of large and complex systems-on-chip with less costs and higher performances. [ABSTRACT FROM PUBLISHER]

This research is purposed to increase computer function into a time driven to support real time system so that the processor can work according to determined time variable and can work optimally in a certained deadline. The first approachment of this research is a processor which has a priority arbiter/border of a task. The second approachment, is a numerator processor with variable precision (VP) computing. The third approachment is by functioning statistic control of the emergence task that will be observing with the help of coprocessor which is placed in the front section of bitspace architecture of the second approachment above. The last aprroachment is by adding certainty precision in form of arithmetic interval that is able to cut the data/task. The data/task-cut is in the form of upper and lower border from the bounds. These four approachments can be structured orthoganally or stand alone into a processor/several processors. Initial hyphothesis of these four approachments can produce a processor that can work optimally in time variable and in a fast, accurate, reliable and robust daedline in supporting real time data/task finishing. [ABSTRACT FROM PUBLISHER]

Heterogeneous architectures, where a multicore processor, which is optimized for fast single-thread performance, is accompanied with a large number of simpler, but more power-efficient cores optimized for parallel workloads, such as NVIDIA's GPUs or Intel's Many Integrated Core (MIC), have been receiving a lot attention recently. Although NVIDIA's GPUs include built-in support for parallelism control, the MIC uses classical software thread creation and scheduling done by the operating system (OS). While efficient thread creation is desired in such many-core environments, current OS APIs provide the facility of creating only one thread at a time. In this paper, we propose a new system call for parallel thread creation on many-core coprocessors and show that it can perform up to 6.9 times better than the sequential version when executed on Intel's MIC software development platform. [ABSTRACT FROM PUBLISHER]

Aiming at the issues of slow speed and low security of the removable storage equipment nowadays, this paper proposed a high performance cipher SoC. It integrates an special-designed cipher coprocessor which can realize kinds of cryptographic algorithms. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH)error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. Based on the architecture of Nand Flash Controller, this paper proposed techniques to accelerate the access speed of NAND Flash. The result verified by the development board shows that the proposed SoC can improve the data access performance in both read and program operation of NAND Flash. The built-in coprocessor can support cipher operations with high security, high flexibility and high data throughput. [ABSTRACT FROM PUBLISHER]

Java Card Coprocessor is used for implementing Java Card Virtual Machine by hardware. Java Card needs to run with low power consumption, especially in the field of contactless Java Card. In this paper, a previous designed Java Card Coprocessor[2] is analyzed. This paper mainly focuses on the hardware implementation of the instruction set for Java Card Virtual Machine and its disadvantages. In order to reduce the power consumption, a novel instruction classification of Java Card Virtual Machine has been achieved. And because Java Card Virtual Machine is based on stack operation, a new operand stack is designed by changing the width of the operand stack to reduce the instruction execute times, the new Java Card Coprocessor is 40% faster than previous one at the same frequency. So we can reduce the frequency by 40% while operating the same instruction in the same time. The novel Java Coprocessor has been implemented by hardware and verified by FPGA. The power consumption of the novel Java Coprocessor is about 40% lower than the previous one. [ABSTRACT FROM PUBLISHER]

DCFA-MPI is an MPI library implementation for manycore-based clusters, whose compute node consists of Intel MIC (Many Integrated Core) connected to the host via PCI Express with InfiniBand. DCFA-MPI enables direct data transfer between MIC units without the host assist. MPI_Init and MPI_Finalize functions are offloaded to the host side in order to initialize the InfiniBand HCA and inform its PCI-Express address to MIC. MPI communication primitives executed in MIC may transfer data directly to other MICs or hosts by issuing commands to HCA. The implementation is based on the Mellanox InfiniBand HCA and Intel's Knights Ferry, and compared with the Intel MPI + offload mode. Preliminary results show that DCFA-MPI outperforms the Intel MPI + offload mode by 1.12 ~ 5 times. [ABSTRACT FROM PUBLISHER]

DCFA-MPI is an MPI library implementation for manycore-based clusters, whose compute node consists of Intel MIC (Many Integrated Core) connected to the host via PCI Express with InfiniBand. DCFA-MPI enables direct data transfer between MIC units without the host assist. MPI_Init and MPI_Finalize functions are offloaded to the host side in order to initialize the InfiniBand HCA and inform its PCI-Express address to MIC. MPI communication primitives executed in MIC may transfer data directly to other MICs or hosts by issuing commands to HCA. The implementation is based on the Mellanox InfiniBand HCA and Intel's Knights Ferry, and compared with the Intel MPI + offload mode. Preliminary results show that DCFA-MPI outperforms the Intel MPI + offload mode by 1.12 ~ 5 times. [ABSTRACT FROM PUBLISHER]

Heterogeneous architectures, where a multicore processor is accompanied with a large number of simpler, but more power-efficient CPU cores optimized for parallel workloads, are receiving a lot of attention these days. Currently, these co-processors come with a limited on-board memory, which requires partitioning computational problems manually into pieces that can fit into the device's RAM as well as overlapping computation and communication. In this poster we propose application transparent, operating system (OS) assisted hierarchical memory management system, where the OS orchestrates data movement between the host and the device and updates the process virtual memory address space accordingly. We identify the main scalability issues of frequent address space changes, such as the increasing price of TLB invalidations with the growing number of CPU cores and propose partially separated page tables to overcome the problem. With partially separated page tables each core maintains its own set of mappings of the computation area, enabling the OS to perform address space updates in a scalable manner, and involve a particular CPU core in TLB invalidation only if it is absolutely necessary. Furthermore, we propose dedicated data movement cores in order to efficiently overlap computation and communication. We provide experimental results on stencil computation, a common HPC kernel. [ABSTRACT FROM PUBLISHER]