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NREL and Corning Incorporated have collaborated on a project to investigate the effect of increasing CdTe deposition temperature on device performance. CdTe deposition temperatures are generally limited by the thermal properties of the glass superstrate. Soda-lime glass is frequently used in commercial production of CdTe, but the low strain point (∼515°C) requires deposition temperatures of 550°C or below. While the CdTe industry has enjoyed great success with material grown at these relatively low temperatures, there may be significant benefits to higher deposition temperatures enabled by a high strain point glass. To demonstrate the efficiency benefits of a CdTe cell fabricated at higher deposition temperatures, it is necessary to re-optimize the device fabrication process steps for devices made with CdTe films at each deposition temperature. Using Corning, Inc.'s new engineered high-strain-point glass superstrate, we developed a fabrication process optimized for CdTe films deposited at 550° and 600°C. Here, we report details of the fabrication processes that resulted in an absolute efficiency gain of 1.2% for devices fabricated with 600°C CdTe deposition temperature versus 550°C. [ABSTRACT FROM PUBLISHER]

The author investigates and models gate-induced drain leakage (GIDL) effects over a wide variety of drain structures, including n +-As/n--P combinations, n - implant doses (Nn-), and spacer lengths (Ls). An analytical model taking account of nm-order As doping modulation is proposed to explain the enhanced GIDL for n+-As FETs and the suppressed B-B tunneling with increasing Nn- for large-tilt-angle implanted-drain devices. Band-to-defect tunneling via interface states is also simulated and found to limit device performance, as well as hot-carrier reliability, much more severely than B-B tunneling. Based on the above understanding, drain-structure design is discussed in view of both performance and reliability [ABSTRACT FROM PUBLISHER]

A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented [ABSTRACT FROM PUBLISHER]