204 results on '"Endoh, T."'
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2. Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability
3. Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage
4. Scalability of Quad Interface p-MTJ for 1× nm STT-MRAM with 10 ns Low Power Write Operation, 10 Years Retention and Endurance > 1011
5. First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology
6. A novel memory test system with an electromagnet for STT-MRAM testing
7. An Ultra-Low-Power STT-MRAM-Based Multi-Core Associative Coprocessor with Inter-Core Pipeline Scheme for Large-Scale Full-Adaptive Nearest Pattern Search
8. Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm
9. 14ns write speed 128Mb density Embedded STT-MRAM with endurance>1010 and 10yrs retention@85°C using novel low damage MTJ integration process
10. Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system
11. First-Principles Study on Shape Degradation during Oxidation Process for Three-Dimensional Structure Devices
12. Ultralow-Power and Compact Nonvolatile Brain-Inspired VLSIs Based on CMOS/MTJ Hybrid Technology
13. Etch Process Technology for High Density STT-MRAM.
14. High thermal tolerance synthetic ferrimagnetic reference layer with modified buffer layer by ion irradiation for perpendicular anisotropy magnetic tunnel junctions.
15. Cross Point Type 1T-1MTJ STT-MRAM Cell with 60 nm Multi-pillar Vertical Body Channel MOSFET under 55 nm p-MTJ and Its Beyond for High Density STT-MRAM
16. Guiding principles for the fabrication of V-MOSFETs based on a Si emission model
17. Sub 1 V 60 nm Vertical Body Channel MOSFET Based 6T SRAM Array with Wide Noise Margin and Excellent Power Delay Product
18. Highly Efficient and Compact CMOS DC-DC Converter with Novel Transistor Layout of 60 nm Multi-pillar Type Vertical Body Channel MOSFET
19. A Study of Validation of an Evaluation Model of Accurate Thermal Stability Factor for MTJs Using Its Thermal Dependency
20. Impact of sputtering condition for tungsten on magnetic and transport properties of magnetic tunneling junction with CoFeB/W/CoFeB free layer
21. Novel Integrated Voltage Regulators with High-Side NMOS Power Switch and Dedicated Bootstrap Driver Using Vertical MOSFET for Efficiency Enhancement
22. New Model of Switching Delay Induced by Modulation Effect of Damping and STT Pumping Balance with Programing Current and Interference Phenomena in p-MTJ Array
23. Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme
24. Study about the Ion Beam Etching (IBE) Process for the High Density Spintronic Devices and its Damage Recovery by the Oxygen Showering Post-treatment (OSP)
25. A Compact and Ultra-Low-Power STT-MRAM-Based Associative Memory for Nearest Neighbor Search with Full Adaptivity of Template Data Format Employing Current-Mode Similarity Evaluation and Time-Domain Minimum Searching
26. Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design
27. Optimization of CoFeB Capping Layer Thickness for Characterization of Leakage Spot in MgO Tunneling Barrier of Magnetic Tunnel Junction
28. A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme
29. 10 nm p-MTJ Array Design for Suppressing Switching Delay Induced by Interference Due to Magnetic Dipole Interaction for High Density STT-MRAM
30. Universal Damage Recovery Scheme using the Oxygen Showering Post-treatment (OSP) Process for Sub-20nm High Density STT-MRAM Devices
31. First-Principles Study on Hydrogen Annealing Effect in Si/SiO2 Interface by Thermal Oxidation
32. Novel Design of Electrostatic Lens Potential for Improving Bending Curvature and Transmission Probability of Drive Current for Vertical Body Channel MOSFET
33. Effect of series resistance on dielectric breakdown phenomenon of silicon carbide MOS capacitor
34. 10 nm\phi perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction with over 400°C high thermal tolerance by boron diffusion control
35. Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure
36. Novel oxygen showering process (OSP) for extreme damage suppression of sub-20nm high density p-MTJ array without IBE treatment
37. Diffusion behaviors observed on the surface of CoFeB film after the natural oxidation and the annealing
38. Perpendicular-anisotropy CoFeB-MgO based magnetic tunnel junctions scaling down to 1X nm
39. Study about the Process Damage Mechanism of the Patterned Interface Perpendicular Magnetic Tunnel Juncotions (MTJs) by Hydrogen Ion Treatments
40. Properties of Perpendicular-Anisotropy Magnetic Tunnel Junctions Fabricated over The Cu Via
41. A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation
42. Impact of Sub-Volume Excitation for Improving Overdrive Delay Product in Sub-40nm p-MTJ and Its Beyond
43. Ultra Low-Frequency Noise in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process
44. A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit
45. A High-frequency Level-up Shifter Based on 0.18μm Vertical MOSFETs with More than 70% Reduction of Overshoot-voltage Above VDD
46. LLG Micromagnetic Simulation on STT Efficiency of sub 30nm Perpendicular MTJs with etching damage
47. A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
48. Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications
49. Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell
50. A 4x4 Nonvolatile Multiplier Using Novel MTJ-CMOS Hybrid Latch and Flip-Flop
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