13 results on '"Eugene Koskin"'
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2. Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process.
3. FPGA Validation of Event-Driven ADPLL.
4. Synchronisation in Noisy PLL Networks: Time Domain Model and its Analysis.
5. Electrostatic Control and Entanglement of CMOS Position-Based Qubits.
6. Simulation Methodology for Electron Transfer in CMOS Quantum Dots.
7. Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation.
8. All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.
9. Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs.
10. Semianalytical model for high speed analysis of all-digital PLL clock-generating networks.
11. Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks.
12. Mode-locking in a network of kuramoto-like oscillators.
13. Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks.
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