18 results on '"Fangxu Lv"'
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2. An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.
3. A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.
4. Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.
5. A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.
6. An Adaptive Equalization Algorithm for High Speed SerDes.
7. An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.
8. A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.
9. A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.
10. A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology.
11. Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
12. An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.
13. A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
14. A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.
15. A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.
16. A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.
17. A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
18. Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.
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