7 results on '"Gerd Ritter"'
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2. Formale Verifikation der Register-Allokation.
3. Sequential Equivalence Checking by Symbolic Simulation.
4. Formal Verification of Descriptions with Distinct Order of Memory Operations.
5. Formal Verification of Designs with Complex Control by Symbolic Simulation.
6. Automatic Verification of Scheduling Results in High-Level Synthesis.
7. Automatische Synthese und Verifikation von RISC-Prozessoren.
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