43 results on '"Gray, C. Thomas"'
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2. An Energetic Approach to Task-Invariant Ankle Exoskeleton Control.
3. A Compact, Two-Part Torsion Spring Architecture.
4. Convex Optimization for Spring Design in Series Elastic Actuators: From Theory to Practice.
5. Biologically-Inspired Impedance Control With Hysteretic Damping.
6. Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications
7. A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode
8. Adaptive Compliance Shaping with Human Impedance Estimation.
9. Robust Estimator-Based Safety Verification: A Vector Norm Approach.
10. Methods for Measuring the Just Noticeable Difference for Variable Stimuli: Implications for Perception of Metabolic Rate with Exoskeleton Assistance.
11. Complex Stiffness Model of Physical Human-Robot Interaction: Implications for Control of Performance Augmentation Exoskeletons.
12. Modeling and Loop Shaping of Single-Joint Amplification Exoskeleton with Contact Sensing and Series Elastic Actuation.
13. Exploiting the Natural Dynamics of Series Elastic Robots by Actuator-Centered Sequential Linear Programming.
14. Safety Control Synthesis with Input Limits: a Hybrid Approach.
15. MIMO identification of frequency-domain unreliability in SEAs.
16. Analyzing achievable stiffness control bounds of robotic hands with coupled finger joints.
17. A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
18. Towards computationally efficient planning of dynamic multi-contact locomotion.
19. A method for dynamically balancing a point foot robot.
20. Fully omnidirectional compliance in mobile robots via drive-torque sensor feedback.
21. Continuous cyclic stepping on 3D point-foot biped robots via constant time to velocity reversal.
22. A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
23. An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
24. AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
25. Hybrid multi-contact dynamics for wedge jumping locomotion behaviors.
26. A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop
27. 6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
28. Simba
29. A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology
30. Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
31. A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
32. Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
33. A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET
34. Hardware-Enabled Artificial Intelligence
35. Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
36. A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module
37. A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
38. Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.
39. A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors
40. Current parking regulator for zero droop/overshoot load transient response
41. 8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring
42. A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs
43. A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications.
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