90 results on '"Haendler, S."'
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2. Impact of Gamma irradiation on advanced Si/SiGe:C BiCMOS technology: comparison versus X-ray
3. Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
4. 28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications
5. Effects of Total Ionizing Dose on 1-V and Low Frequency Noise characteristics in advanced Si/SiGe:C Heterojunction Bipolar Transistors
6. Reliability assessment of 4GSP/s interleaved SAR ADC
7. Characterization, modeling and comparison of 1/f noise in Si/SiGe:C HBTs issued from three advanced BiCMOS technologies
8. Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies
9. Low Frequency Noise in advanced 55nm BiCMOS SiGeC Heterojunction Bipolar Transistors: Impact of collector doping
10. 28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications
11. Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs
12. Low frequency noise temperature measurements in SiGe:C heterojunction bipolar transistors
13. Hot carrier degradation mechanisms of short-channel FDSOI n-MOSFETs
14. Measurement and characterization of low frequency noise collector current in 0.13 μm SiGe:C HBTs
15. Full front and back gate voltage range method for the parameter extraction of advanced FDSOI CMOS devices
16. Low frequency noise statistical characterization of 14nm FDSOI technology node
17. A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives
18. Study of low frequency noise in advanced SiGe:C heterojunction bipolar transistors
19. Statistical analysis of dynamic variability in 28nm FD-SOI MOSFETs
20. Characterization and modeling of low frequency noise in 0.13 µm BiCMOS SiGe:C heterojunction bipolar trasnsistors
21. The impact of high Vth drifts tail and real workloads on SRAM reliability
22. Low frequency noise temperature measurements in SiGe:C heterojunction bipolar transistors.
23. Measurement and characterization of low frequency noise collector current in 0.13 μm SiGe:C HBTs.
24. Low frequency noise measurements of advanced BiCMOS SiGeC Heterojunction Bipolar Transistors used for mm-Wave to terahertz applications
25. Evolution of low frequency noise and noise variability through CMOS bulk technology nodes
26. Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
27. Characterization and Modeling of Back Bias Impacts on Remote-Coulomb-Limited Mobility in UTBB-FDSOI Devices
28. Front-back gate coupling effect on 1/f noise in ultra-thin Si film FDSOI MOSFETs
29. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates
30. 28nm FDSOI technology platform for high-speed low-voltage digital applications
31. Impact of 45° rotated substrate on UTBOX FDSOI high-k metal gate technology
32. Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances
33. Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology
34. Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors
35. Improvement of 1/f noise in advanced 0.13 µm BiCMOS SiGe:C Heterojunction Bipolar Transistors
36. Low power UTBOX and back plane (BP) FDSOI technology for 32nm node and below
37. Oxide defects generation modeling and impact on BD understanding
38. Efficient multi-VT FDSOI technology with UTBOX for low power circuit design
39. First CMOS integration of ultra thin body and BOX (UTB2) structures on bulk direct silicon bonded (DSB) wafer with multi-surface orientations
40. Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
41. Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
42. Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node
43. Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications
44. FDSOI devices with thin BOX and ground plane integration for 32nm node and below
45. RF Power NLDMOS Technology Transfer Strategy from the 130nm to the 65nm node on thin SOI
46. Thermal resistance reduction in power MOSFETs integrated in a 65nm SOI technology
47. Silicon characterization of standby leakage reduction techniques in a 0.13μm Low Power Partially-Depleted Silicon-On-Insulator Technology
48. ON THE 1/F NOISE IN FULLY DEPLETED SOI TRANSISTORS
49. On the Noise in Dynamic Threshold (DT) MOS/SOI Transistors.
50. Thorough Investigation of Kink-Related Excess Noise in Deep Submicron SOI N-MOSFETs on Unibond Substrate
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