211 results on '"Horowitz, M"'
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2. Post-fabrication wavelength trimming of fiber Bragg gratings by using a 213-nm 8-ps pulsed laser
3. Intermediate representations for controllers in chip generators
4. Theoretical and experimental study of single and dual-loop optoelectronic oscillators
5. Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links
6. A 24Gb/s Software Programmable Multi-Channel Transmitter
7. A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications
8. Low cost dispersion sign monitor for 40Gb/s systems
9. Latency Sensitive FMA Design.
10. H.264 hierarchical P coding in the context of ultra-low delay, low complexity applications.
11. Spurious-mode suppression in optoelectronic oscillators.
12. Loop-length dependent sources of phase noise in optoelectronic oscillators.
13. An integrated framework for joint design space exploration of microarchitecture and circuits.
14. Intent-leveraged optimization of analog circuits via homotopy.
15. Fortifying analog models with equivalence checking and coverage analysis.
16. Session details: Reshaping EDA for power
17. A new inverse scattering algorithm for reconstructing highly reflecting fiber Bragg gratings
18. Experimental and simulation study of dual injection-locked OEOs.
19. An analytical model of the dual-injection-locked opto-electronic oscillator (DIL-OEO).
20. Energy-performance tunable logic.
21. In field, energy-performance tunable FPGA architectures.
22. Verification of chip multiprocessor memory systems using a relaxed scoreboard.
23. Processor Performance Modeling using Symbolic Simulation.
24. A high-speed, low-power 3D-SRAM architecture.
25. Robust Energy-Efficient Adder Topologies.
26. A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects.
27. Integrated Regulation for Energy-Efficient Digital Circuits.
28. Improving CDR Performance via Estimation.
29. High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects.
30. A 1.6 Gb/s, 3 mW CMOS receiver for optical communication
31. A new method for design of robust digital circuits.
32. Scalable circuits for supply noise measurement.
33. CMOS transceiver with baud rate clock recovery for optical interconnects.
34. Burst mode packet receiver using a second order DLL.
35. 20Gb/s 0.13μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer.
36. Circuits and techniques for high-resolution measurement of on-chip power supply noise.
37. A framework for designing reusable analog circuits.
38. Efficient on-chip global interconnects.
39. Specifying and verifying hardware for tamper-resistant software.
40. Modeling and analysis of high-speed links.
41. Optimizing the mapping of low-density parity check codes on parallel decoding architectures.
42. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers.
43. 428. Regulatory Impact of an Investigation into a Hazardous Waste Confined Space Accident
44. Interrogation of fiber gratings using spectral interferometry of a low-coherence light source
45. 354. Aspects of Decommissioning a Semiconductor R&D Facility
46. The Stanford FLASH multiprocessor
47. Coupling effects in saturable gain media with interfering coherent optical amplifier pump beams
48. Noiselike generation in erbium-doped fiber lasers due to nonlinear polarization rotation in birefringent fibers
49. Third harmonic generation for nonlinear scanning laser microscopy
50. Using partitioning to help convergence in the standard-cell design automation methodology.
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