15 results on '"Jullian, S."'
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2. Highly Manufacturable and Cost-effective Single TaxC / HfxZr(1-x)O2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond
3. Integration of multi-level self-aligned CoWP barrier compatible with high performance BEOL
4. Effect of Process Induced Strain in 35 nm FDSOI Devices with Ultra-Thin Silicon Channels
5. Strained-Si for CMOS 65nm node : Si0.8Ge0.2 SRB or “Low Cost” approach ?
6. MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances.
7. Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS.
8. High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate.
9. Implementing Convection in a Reservoir Simulator: A Key Feature in Adequately Modeling the Exploitation of the Cantarell Complex
10. Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS
11. 0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
12. High performance 40 nm nMOSFETs with HfO/sub 2/ gate dielectric and polysilicon damascene gate
13. Highly performant double gate MOSFET realized with SON process
14. MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
15. A conventional 45mn CMOS node low-cost platform for general purpose and low power applications
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