162 results on '"Kim, Tony"'
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2. A Dynamic Gesture Recognition Algorithm Using Single Halide Perovskite Photovoltaic Cell for Human-Machine Interaction
3. Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory
4. A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations
5. An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory
6. 282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing
7. A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing
8. A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates
9. DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC
10. A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions
11. A Local Transpose 9T SRAM Compute-In-Memory Macro with Programmable Single-Slope SAR ADC
12. A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation
13. A Low-Power Gesture Recognition System utilizing Hybrid Tiny Classifiers
14. A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process
15. A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method
16. A 181µW Real-Time 3-D Hand-Gesture Recognition System for Edge Applications
17. A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
18. A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering
19. FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems
20. A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement
21. A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking
22. A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC
23. A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications
24. An Ultra-Low-power Real-Time Hand-Gesture Recognition System for Edge Applications
25. A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory
26. AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing
27. A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme
28. 9.7 A 184 µ W Real-Time Hand-Gesture Recognition System with Hybrid Tiny Classifiers for Smart Wearable Devices
29. ReRAM Device and Circuit Co-Design Challenges in Nano-scale CMOS Technology
30. A Low-Power Smart Gesture Sensing SoC with On-chip Image Sensor for Smart Devices
31. Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks
32. A Secure Data-Toggling SRAM for Confidential Data Protection
33. Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing
34. Design and Characterization of Radiation-Hardened MCU for Space Application using Error Correction SRAM and Glitch Removal Clock Buffer Cell
35. A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length
36. A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC
37. A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks
38. Overview of Memory Design for Next Generation Applications
39. Modelling of Phase Change Memory(PCM) cell for Circuit Simulation
40. Continuous wave laser excitation based portable optoacoustic imaging system for melanoma detection
41. A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm
42. A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation
43. P766 Slings and arrows of syphilis surveillance: the department of defense experience with administrative case finding
44. A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks
45. A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space
46. Development of PCM and OTS Macro-models for HSPICE Compatible Simulation
47. Novel current-mirror based time dependent sense scheme for MLC PRAM
48. An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist
49. Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects
50. An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm
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