216 results on '"Kuroda, Tadahiro"'
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2. A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
3. A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
4. A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
5. A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
6. A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
7. A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
8. A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias
9. A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
10. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
11. An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique
12. Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
13. A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
14. A Physical Verification Methodology for 3D-ICs Using Inductive Coupling
15. A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
16. A bonding-less 5-GHz RFID module using a 300um x 500um IC chip
17. CA2 area detection from hippocampal microscope images using deep learning
18. An on-chip antenna with an area of 0.9 square millimeters for RFID applications in the 5.8 GHz – 24 GHz range
19. A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
20. Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface
21. Communication Distance Enhancement of Transmission Line Coupler by Using Parallelized Driver ICs
22. Crosstalk Analysis and Countermeasures of High-Density Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory
23. A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS
24. 3D Integration of Ka-band RFIC by Inductive Interchip Wireless Communication Using Figure-8 Coils
25. A Transmission Line Coupler Component for direct B2B communications
26. A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes
27. Circuit and Package Co-design for 3D Integration
28. Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming
29. 3D System Integration in a Package for Artificial Intelligence
30. Balanced Mini-Batch Training for Imbalanced Image Data Classification with Neural Network
31. Wireless Power Transfer System for 3-D stacked Multiple Receivers Switching between Single and Dual Frequency Modes
32. Comparative Performance Analysis of Dual-Rail Domino Logic and CMOS Logic Under NearThreshold Operation
33. An Electrically Small On-Chip Antenna Scaled down to One-Twentyfifth by One-Fiftieth of Wavelength
34. Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS
35. An EMI-less full-bridge inverter for high speed SiC switching devices
36. QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
37. Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers
38. Convolutional neural network for industrial egg classification
39. Building block multi-chip systems using inductive coupling through chip interface
40. An inductive-coupling link for 3-D Network-on-Chips
41. A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface
42. Wireless power transfer to stacked modules for IoT sensor nodes
43. BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
44. A 6Gb/s rotatable non-contact connector with high-speed/I2C/CAN/SPI interface bridge IC
45. System integration in a package for cloud and edge
46. An image sensor/processor 3D stacked module featuring ThruChip interfaces
47. Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface
48. An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips
49. Basic study of non-contact connector for high-speed space cable transmission: Space fibre, short paper
50. Low-energy algorithm for self-controlled Wireless Sensor Nodes
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