34 results on '"Riener, Heinz"'
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2. A Versatile Mapping Approach for Technology Mapping and Graph Optimization
3. Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis
4. Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database
5. Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition
6. From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++
7. Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies
8. Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits
9. Automatic Uniform Quantum State Preparation Using Decision Diagrams
10. Revisiting Explicit Enumeration for Exact Synthesis
11. Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle
12. A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
13. Exact DAG-Aware Rewriting
14. Exact Synthesis of LTL Properties from Traces
15. Scalable Generic Logic Synthesis
16. On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis
17. Design Understanding: From Logic to Specification
18. Size Optimization of MIGs with an Application to QCA and STMG Technologies
19. Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model
20. Mining Latency Guarantees for RTL Designs
21. Scalable Generic Logic Synthesis: One Approach to Rule Them All.
22. CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification
23. Exact diagnosis using boolean satisfiability
24. WCET overapproximation for software in the context of a Cyber-Physical System
25. Equivalence checking on ESL utilizing a priori knowledge
26. Designing reliable cyber-physical systems overview associated to the special session at FDL'16
27. Counterexample-guided diagnosis
28. Equivalence Checking on System Level Using a Priori Knowledge
29. MetaSMT: a unified interface to SMT-LIB2
30. Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
31. Model-based diagnosis versus error explanation
32. Test Case Generation from Mutants Using Model Checking Techniques
33. Improving fault tolerance utilizing hardware-software-co-synthesis.
34. SMT-Based CPS Parameter Synthesis
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