41 results on '"Roberto Guerrieri"'
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2. Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wire.
3. Characterization of chip-to-chip wireless interconnections based on capacitive coupling.
4. 3D system on chip memory interface based on modeled capacitive coupling interconnections.
5. 3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation.
6. Chip-to-chip communication based on capacitive coupling.
7. System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface.
8. RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.
9. 3D Capacitive Interconnections for High Speed Interchip Communication.
10. 3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities.
11. Yield prediction for 3D capacitive interconnections.
12. Design and implementation of a reconfigurable heterogeneous multiprocessor SoC.
13. Low leakage design of LUT-based FPGAs.
14. Electrical measurement of alignment for 3D stacked chips.
15. Studying skin ageing through wavelet-based analysis of capacitive images.
16. Beyond the microscope: embedded detectors for cell biology applications.
17. A 0.14mW/Gbps high-density capacitive interface for 3D system integration.
18. In Vivo Quantitative Evaluation of Skin Ageing by Capacitance Image Analysis.
19. A XiRisc-based SoC for embedded DSP applications.
20. Word endpoints detection in the presence of non-stationary noise.
21. Very low complexity prompted speaker verification system based on HMM-modeling.
22. Low power techniques for flash memories.
23. A system-on-chip for pressure-sensitive fabric.
24. A low-power system-on-chip for the documentation of road accidents.
25. OMI-Compliant Model for Virtual Emulation.
26. A 1 V, 25 μW speech recognizer for portable systems.
27. A 35 μW 1.1 V gate array 8×8 IDCT processor for video-telephony.
28. A low-power VLSI feature extractor for speech recognition.
29. Fast board-level prototyping of a speech recognition system using virtual emulation.
30. Extraction of LP-based features from one-bit quantized speech signals for recognition purposes.
31. A smoothly upgradable approach to virtual emulation of HW/SW systems.
32. A VLSI array processor accelerator for k-NN classification.
33. A 2D-DCT low-power architecture for H.261 coders.
34. An array-processor based architecture for classification problems.
35. Highly-constrained neural networks with application to visual inspection of machined parts.
36. A novel metric for nearest-neighbor classification of hand-written digits.
37. Triangular matrix inversion on Graphics Processing Unit.
38. New Perspectives and Opportunities From the Wild West of Microelectronic Biochips.
39. Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy?
40. Measuring Skin Topographic Structures through Capacitance Image Analysis.
41. A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
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