99 results on '"Ryynanen, Jussi"'
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2. A 0.8-6 GHz True-Time-Delay Beam-Nulling Receiver Front-End
3. A 6–20 GHz 400-MHz Modulation-Bandwidth CMOS Transmitter IC
4. A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps
5. A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period
6. Design of Cyclic-Coupled Ring Oscillators with Guaranteed Maximal Phase Resolution
7. Energy-Efficient Array Transmitters Through Outphasing and Over-the-Air Combining
8. A Transmitter IC with Supply Tuning for Frequency-Reconfigurable Antenna Cluster
9. Characterization of an Antenna Cluster and Transmitter IC with a Modulated Signal
10. A 5.4-GHz 2/3/4-Modulus Fractional Frequency Divider Circuit in 28-nm CMOS
11. A Compact Low-Power 140-GHz Low-Noise Amplifier with 19-dB Gain and 7-dB NF
12. A Frequency Tunable MIMO Antenna Cluster with Transmitter IC
13. A 30-GHz Switched-Capacitor Power Amplifier for 5G SoCs
14. A 3.5-GHz Digitally-Controlled Open-Loop Fractional-N Frequency Divider in 28-nm CMOS
15. Injection Locking of Ring Oscillators with Digitally Controlled Delay Modulation
16. A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS
17. A Sensor Interface for Neurochemical Signal Acquisition
18. A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End
19. A VCO-based ADC with Relaxation Oscillator for Biomedical Applications
20. A 20-60GHz Digitally Controlled Composite Oscillator for 5G
21. A Low-Power Hardware Stack for Continuous Data Streaming from Telemetry Implants
22. A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators
23. A 3-43ps time-delay cell for LO phase-shifting in 1.5-6.5GHz beamsteering receiver
24. A 30-dBm Class-D Power Amplifier with On/Off Logic for an Integrated Tri-Phasing Transmitter in 28-nm CMOS
25. Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End
26. Full-Duplex Wireless Transceiver Self-Interference Cancellation Through FD-SOI Buried-Gate Signaling
27. Spectral Effects of Discrete-Time Amplitude Levels in Digital-Intensive Wideband Radio Transmitters
28. Dynamic element matching in digital-to-analog converters with code-dependent output resistance
29. Open-loop all-digital delay line with on-chip calibration via self-equalizing delays
30. A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching
31. A charge limiting and redistribution method for delay line locking in multi-output clock generation
32. 13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth
33. 13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping
34. Reference receiver enabled digital cancellation of nonlinear out-of-band blocker distortion in wideband receivers
35. A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures
36. Multilevel outphasing power amplifier system with a transmission-line power combiner
37. Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter
38. Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction
39. Session 20 overview: RF-to-THz transceiver techniques
40. A 0.8–3 GHz mixer-first receiver with on-chip transformer balun in 65-nm CMOS
41. All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter
42. The synthesis of noise transfer functions for bandpass delta-sigma modulators with tunable center frequency
43. A wideband under-sampling blocker detector with a 0.7–2.7 GHz mixer-first receiver
44. A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator
45. A 1.2 – 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS
46. Measurement campaign for collaborative sensing using cyclostationary based mobile sensors
47. 28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS
48. Digital linearization of direct-conversion spectrum sensing receiver
49. The synthesis of noise transfer functions for bandpass delta-sigma modulators with tunable center frequency.
50. All-digital phase-locked loop in 40 nm CMOS for 5.8 Gbps serial link transmitter.
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