25 results on '"Se-Joong Lee"'
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2. A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
3. SILENT: serialized low energy transmission coding for on-chip interconnection networks.
4. On-chip network based embedded core testing.
5. A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer.
6. A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
7. A distributed crossbar switch scheduler for on-chip networks.
8. A practical method to use eDRAM in the shared bus packet switch.
9. A 670 ps, 64 bit dynamic low-power adder design.
10. One chip-low power digital-TCXO with sub-ppm accuracy.
11. A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
12. Low energy transmission coding for on-chip serial communications.
13. Networks-on-chip and Networks-in-Package for High-Performance SoC Platforms.
14. Adaptive network-on-chip with wave-front train serialization scheme.
15. A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth.
16. Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications.
17. A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip.
18. A novel high speed low power logic family: Race logic.
19. 7.1 GB/sec bandwidth 3D rendering engine using the EML technology.
20. A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications.
21. A 7.1 GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS.
22. Low energy transmission coding for on-chip serial communications.
23. 480 ps 64-bit race logic adder.
24. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform.
25. An 800MHz star-connected on-chip network for application to systems on a chip.
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