16 results on '"Taha Soliman"'
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2. CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions.
3. AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures.
4. Error Detection and Correction Codes for Safe In-Memory Computations.
5. Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators.
6. SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators.
7. Simulation-driven Latency Estimations for Multi-core Machine Learning Accelerators.
8. FeFET versus DRAM based PIM Architectures: A Comparative Study.
9. Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators.
10. Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators.
11. Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design.
12. A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.
13. Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators.
14. Efficient FeFET Crossbar Accelerator for Binary Neural Networks.
15. A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks.
16. Fast validation of DRAM protocols with timed petri nets.
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