97 results on '"WANG Chun-yao"'
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2. An Efficient Approach to Iterative Network Pruning
3. Minimizing Computation in Binarized Neural Network Inference using Partial-Filter Sharing
4. Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices
5. A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
6. A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli
7. Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee
8. Overview of 2022 CAD Contest at ICCAD
9. An Approach to Unlocking Cyclic Logic Locking
10. Overview of 2021 CAD Contest at ICCAD
11. Cluster Tool Performance Analysis using Graph Database
12. An IMU-aided Fitness System
13. On Reduction of Computations for Threshold Function Identification
14. On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays
15. A General Equivalence Checking Framework for Multivalued Logic
16. An Efficient Approximate Node Merging with an Error Rate Guarantee
17. A Dynamic Expansion Order Algorithm for the SAT-based Minimization
18. Rehabilitation System for Limbs using IMUs
19. A Convolutional Result Sharing Approach for Binarized Neural Network Inference
20. Empirical Study of Multi-Objective Parameter Optimization in Wire Bonding Process
21. A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises
22. A Glitch Key-Gate for Logic Locking
23. A Data Mining Approach for Optimizing Manufacturing Parameters of Wire Bonding Process in IC Packaging Industry and Empirical Study
24. Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
25. A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification
26. Using range-equivalent circuits for facilitating bounded sequential equivalence checking
27. Efficient synthesis of approximate threshold logic circuits with an error rate guarantee
28. Logic optimization with considering boolean relations
29. In&Out: Restructuring for threshold logic network optimization
30. Majority logic circuits optimisation by node merging
31. Concept Mining to Chinese News Similarity Measure
32. MajorSat: A SAT solver to majority logic
33. CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction
34. Synthesis and verification of cyclic combinational circuits
35. Using Structural Relations for Checking Combinationality of Cyclic Circuits
36. A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays
37. The Interaction between Contacting Barrier Materials for Containment of Radioactive Wastes
38. BDD-based synthesis of reconfigurable single-electron transistor arrays
39. Alzheimer's disease classification based on gait information
40. Width minimization in the Single-Electron Transistor array synthesis
41. Rewiring for threshold logic circuit minimization
42. Sensitization criterion for threshold logic circuits and its application
43. Using structural relations for checking combinationality of cyclic circuits.
44. On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques
45. CA-ABAC: Class Algebra Attribute-Based Access Control
46. Width minimization in the Single-Electron Transistor array synthesis.
47. Rewiring for threshold logic circuit minimization.
48. Sensitization criterion for threshold logic circuits and its application.
49. Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer
50. On rewiring and simplification for canonicity in threshold logic circuits
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