33 results on '"Zhao, Qing-Tai"'
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2. High Performance 5 nm Si Nanowire FETs with a Record Small SS = 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain
3. Vertical GeSn/SiGeSn GAA Nanowire n-FETs with High Electron Mobility
4. Ferroelectric Schottky Barrier MOSFET as Analog Synapses for Neuromorphic Computing
5. GeSn Vertical Gate-all-around Nanowire n-type MOSFETs
6. Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory
7. NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future
8. 4-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses
9. Impact of the Backgate on the Performance of SOI UTBB nMOSFETs at Cryogenic Temperatures
10. Vertical Heterojunction Ge0.92 Sn0.08 /Ge GAA Nanowire pMOSFETs: Low SS of 67 mV/dec, Small DIBL of 24 mV/V and Highest Gm,ext of 870 μS/μm
11. First Demonstration of Vertical Ge0.92Sn0.08/Ge and Ge GAA Nanowire nMOSFETs with Low SS of 66 mV/dec and Small DIBL of 35 mV/V
12. Vertical Heterojunction Ge0.92Sn0.08/Ge Gate-All-Around Nanowire pMOSFETs
13. Subthreshold Behavior of MFMIS and MFIS Transistors caused by Ferroelectric Polarization Switching
14. Steep slope negative capacitance FDSOI MOSFETs with ferroelectric HfYOx
15. DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework
16. Ultrathin lateral unidirectional bipolar-type insulated-gate transistor as pH sensor
17. Analog and RF analysis of gate all around silicon nanowire MOSFETs
18. Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices
19. Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation
20. Si n-TFETs on ultra thin body with suppressed ambipolarity
21. Improved NiSi contacts on Si by CF4 plasma immersion ion implantation for 14nm node MOSFETs
22. Investigation of band-to-band tunneling parameters in sige by using MOSFET GIDL current analysis
23. Strained silicon nanowire tunnel FETs and NAND logic
24. Analysis of GeSn-SiGeSn hetero-tunnel FETs
25. Experimental demonstration of improved analog device performance in GAA-NW-TFETs
26. Multi-gates SOI LDMOS for improved on-state performance
27. Experimental demonstration of inverter and NAND operation in p-TFET logic at ultra-low supply voltages down to VDD = 0.15 V
28. Si based tunnel FETs : Status and perspectives
29. Ultrathin Ni silicide contacts on Si and SiGe formed with multi thin Ni/Al layers
30. Si based tunneling field effect transistors and inverters
31. Si based tunnel field effect transistors: Recent achievements.
32. Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI.
33. Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI.
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