120 results on '"Zhigang Mao"'
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2. SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.
3. MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5.
4. A Hierarchical Communication Algorithm for Distributed Deep Learning Training.
5. Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.
6. An Efficient near-Bank Processing Architecture for Personalized Recommendation System.
7. RTMDet-R2: An Improved Real-Time Rotated Object Detector.
8. A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.
9. Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.
10. Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.
11. CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement.
12. Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.
13. Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.
14. Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.
15. A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency.
16. mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.
17. 25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip.
18. MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.
19. Optimizing the data placement and transformation for multi-bank CGRA computing system.
20. Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.
21. Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.
22. A static-placement, dynamic-issue framework for CGRA loop accelerator.
23. Low redundancy matrix-based codes for adjacent error correction with parity sharing.
24. Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.
25. A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.
26. Resource-saving compile flow for coarse-grained reconfigurable architectures.
27. Fault detection and redundancy design for TSVs in 3D ICs.
28. A crosstalk avoidance scheme based on re-layout of signal TSV.
29. Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.
30. A contactless testing methodology for pre-bond interposer.
31. Fault Secure Encoder and Decoder Designs for Matrix Codes.
32. Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.
33. Area and throughput efficient IDCT/IDST architecture for HEVC standard.
34. Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.
35. A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design.
36. TSVs-aware floorplanning for 3D integrated circuit.
37. An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.
38. A cost effective 2-D adaptive block size IDCT architecture for HEVC standard.
39. A soft-output parallel stack algorithm for MIMO detection.
40. Analysis of electromechanical interface model for liquid floated micro-gyroscope.
41. A Block Cipher Circuit Design against Power Analysis.
42. Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.
43. Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures.
44. Contention and energy aware mapping for real-time applications on Network-on-Chip.
45. Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.
46. A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications.
47. A reconfigurable linear array processor architecture for data parallel and computation intensive applications.
48. An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.
49. Robust design of sub-threshold flip-flop cells for wireless sensor network.
50. On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system.
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