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Effective variability support has become an important attribute of modern software development practices. Organizations show an increasing interest in the development of software applications using software platforms, reusable components, and mass customization. Even though many variability management tools exist, an approach that integrates support for variability management (e.g. features, decisions, variation points, and variants) directly into architecture models is still missing. Making variability concepts an integral part of architecture models has many benefits. Variability management and architecture development can be integrated into one consistent information model and development environment supporting full traceability of architectural artifacts (e.g. requirements, features, components) on all levels of the development lifecycle. In this paper we show how we integrated orthogonal variability modeling and feature modeling into LISA, an approach and toolkit for architecture management and analysis. Variability management is no longer a separate activity but an integral part of the architecture development lifecycle. [ABSTRACT FROM PUBLISHER]

The constant increase of subthreshold current of nanometer transistors due to technology scaling may hinder the evolution of high-performance chips in the near future. This evokes the need of accurate leakage power modeling for new nanometer technologies. In this paper, we present an improved subthreshold current model, which was integrated it into an architectural-level power simulator. Using this simulator, we estimated the leakage power in a 2 MB cache memory for 32 nm and 16 nm technology nodes. Our results show that the cache leakage power dissipation for 2 MB 2-way cache at 100 °C fabricated in the 32 nm technology is around 1 W. For the 16 nm technology, we demonstrate the importance of maintaining high threshold voltage to keep leakage power density at the acceptable level. [ABSTRACT FROM PUBLISHER]