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With its multicore technology designed for intensive computation, graphics processing units (GPUs) have advanced tremendously in recent years. The GPU is a multicore coprocessor with dozens or even hundreds of cores designed for intensive computations, unlike a central processing unit (CPU), which has a limited number of cores available. However, CPUs have large caches for accommodating large amounts of data, whereas GPUs have smaller caches but use a massive amount of threads. In order to achieve the best performance from both CPU and GPU, GPU-CPU heterogeneous computing architectures have emerged, resulting in a paradigm shift in parallel computing. Data parallelism, also known as SIMD (single instruction, multiple data), is realized through this paradigm, which allows multiple threads to execute the same task simultaneously on different subsets of the same data. When data parallelism is used to program, it is particularly relevant when there is a lot of data to process, as is often the case in scientific computing. Due to their inherent nature as intensive computing, data parallelism is ideally suited for meta-heuristics. As part of this research, data parallelism is introduced to meta-heuristics, as well as a particular optimization technique called "tiling" in parallel computing. "Tiling" refers to grouping threads into tiles to share access to programmable caches on GPUs in order to improve computation speed, particularly for programs that use the same data repeatedly. We introduce the "tiling" technique to ant colony optimization, a meta-heuristic for solving quadratic assignment problem (QAP). A heterogeneous computing architecture is expected to provide benefits in speed, quality, and efficiency over a CPU alone. [ABSTRACT FROM AUTHOR] more...

With its multicore technology designed for intensive computation, graphics processing units (GPUs) have advanced tremendously in recent years. The GPU is a multicore coprocessor with dozens or even hundreds of cores designed for intensive computations, unlike a central processing unit (CPU), which has a limited number of cores available. However, CPUs have large caches for accommodating large amounts of data, whereas GPUs have smaller caches but use a massive amount of threads. In order to achieve the best performance from both CPU and GPU, GPU-CPU heterogeneous computing architectures have emerged, resulting in a paradigm shift in parallel computing. Data parallelism, also known as SIMD (single instruction, multiple data), is realized through this paradigm, which allows multiple threads to execute the same task simultaneously on different subsets of the same data. When data parallelism is used to program, it is particularly relevant when there is a lot of data to process, as is often the case in scientific computing. Due to their inherent nature as intensive computing, data parallelism is ideally suited for meta-heuristics. As part of this research, data parallelism is introduced to meta-heuristics, as well as a particular optimization technique called "tiling" in parallel computing. "Tiling" refers to grouping threads into tiles to share access to programmable caches on GPUs in order to improve computation speed, particularly for programs that use the same data repeatedly. We introduce the "tiling" technique to ant colony optimization, a meta-heuristic for solving quadratic assignment problem (QAP). A heterogeneous computing architecture is expected to provide benefits in speed, quality, and efficiency over a CPU alone. [ABSTRACT FROM AUTHOR] more...

This work describes a softcore design of a processor in style of Graphic Processing Units. The design is realized using Verilog Hardware Description Language. The proposed design has an advantage in the flexibility to scale up by adding more processing elements to attain more speedup. The design of its instruction set architecture is explained. A realization of four processing elements processor is presented. It requires 268,637 equivalent gates. The maximum frequency is 117 MHz. It is suitable of embedded applications. In term of cycles consumed, it compares very well to a test program running on commercial Intel's CPU, Core2 Duo P8400. [ABSTRACT FROM PUBLISHER] more...

Genetic Algorithms (GAs) are powerful search techniques. However when they are applied to complex problems, they consume large computation power. One of the choices to make them faster is to use a parallel implementation. This paper presents a parallel implementation of Combinatorial Optimisation with Coincidence Algorithm (COIN) on Graphic Processing Units. COIN is a modern GA. It has a wide range of applications. The result from the experiment shows a good speedup in comparison to a sequential implementation on modern processors. [ABSTRACT FROM PUBLISHER] more...

Since biological neural systems contain big number of neurons working in parallel, simulation of such dynamic system is a real challenge. The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level using the high degree of parallelism afforded by graphics processors (GPUs) for large scale SNN with proposed structure in pattern classification field. Simulation results show 100 times speedup for the proposed SNN structure on the GPU compared with the CPU version. In addition, CPU memory has problems when trained for more than 120K cells but GPU can simulate up to 40 million neurons. [ABSTRACT FROM PUBLISHER] more...

As the 4G mobile communication systems require high transmission rate with reliability, the demand for efficient error correcting code increases. In this paper, a novel LDPC (Low Density Parity Check) decoding method is introduced. We address a parallel software implementation of LDPC decoding for CMMB (China Multimedia Mobile Broadcasting) standard. LDPC codes for CMMB employ a regular H-matrix which has the fixed row and column weights. While effectively utilizing the regularity of the H-matrix, we process information on H-matrices for multiple code rates using OpenMP pragmas on a multi-core processor and execute the decoding algorithm in parallel using CUDA (Compute Unified Device Architecture) on a GPU (Graphics Processing Unit). We evaluated the performance of the proposed implementation with respect to two different code rates, and verified that the proposed implementation satisfies the bandwidth requirement for CMMB. [ABSTRACT FROM PUBLISHER] more...

Phase unwrapping refers to the reconstruction process of a continuous phase distribution from a wrapped phase map in optical interferometers, fringe projection systems and synthetic aperture radars. Usually, phase unwrapping (PU) is challenging due to speckle noise, atmosphere interference, and long discontinuities. Two dimensional phase unwrapping algorithms have been developed for several decades including the classic path-following PU algorithm and path independent minimum-norm PU algorithms. Being one of the path-following algorithms, quality-guided phase unwrapping algorithm relies on a quality map to guide the integration path. Recently, quality-guided phase unwrapping algorithm along with WFF processing (WFF-QG) was developed. It can provide better quality map compared with commonly used phase derivative variance (PDV) and largely improve the reliability of quality guided phase unwrapping algorithm. However, the WFF-QG algorithms are computationally expensive, prohibiting it from real-time applications. In this paper, to realize real-time WFF-QG algorithm, we propose a pipelined heterogeneous system based on CPU and graphic processing unit. Using NVIDIA GTX285 graphics card and quad-core 2.5 GHz Intel(R) Xeon(R) CPU E5420, 2.15 frames per second (fps) can be achieved by WFF-QG algorithm for real-time continuous phase retrieval with size 256×256. Moreover, up to 62.3× speedup compared with the sequential codes in the same CPU has been achieved. [ABSTRACT FROM AUTHOR] more...

Deep sub-micron technology enables a high integration of (non-linear) circuit systems for electronic products. In order to design non-linear circuits with guaranteed reliability, a sophisticated simulation procedure is required. However, in existing GPU-enhanced circuit simulation methodologies, numerous data transfers between cores hamper the benefits of GPU computations. In this project, we focus on the parallelization of computations for nonlinear analog/mixed-signal circuit transient simulation. By applying multi-dimensional inverse Laplace Transform, each time-sampled points of the transient response can be computed independently on the GPU architecture. Power-efficient hardware architecture is also explored for a further speedup. With the developed platform, circuit designers can verify circuit's dynamic properties quickly in order to meet the need of time-critical and high-yield designs. [ABSTRACT FROM AUTHOR] more...

Proliferation of social network service permeates lives of people on internet, and its social, political and cultural significance prompts the need to understand and to analyze the contents and structures of such services. The sheer volume of such social network is enormous, and it necessitates development and implementation of efficient social network analysis algorithms. Among these, Influence Maximization is one example of such algorithm. The objective of the influence maximization algorithm is to find a small subset of nodes, so-called seed-nodes, that result in maximization of the spread of influence through the edges in the graph which represents connections in social network. [ABSTRACT FROM PUBLISHER] more...