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The next steps in particle physics will involve colliders that are able to investigate the TeV energy scale so that many of the unanswered questions can be addressed. The Compact Linear Collider (CLIC) aims to do this through collisions of electrons and positrons at a high luminosity and at centre-of-mass energies of up to 3 TeV. In addition to the accelerator, a detector system is under development that targets precision physics measurements in an environment with a high rate of beam-induced backgrounds. One of the sub-detectors that faces particularly challenging requirements is the pixel vertex detector. To achieve its goals, hybrid readout chips either bump-bonded to planar sensors or capacitively coupled to High-Voltage CMOS (HV-CMOS) sensors, fabricated in a commercial 180 nm technology, are under study. Both of these sensor options have a small pitch of 25 x 25 μm2 and are hybridised to 65 nm CLICpix readout ASICs. Initial investigations have shown the feasibility of such technologies, but further, and more detailed studies are needed. This is done through a series of simulations and measurements to assess the suitability of each technology for the CLIC vertex detector. Simulations of the custom designed CCPDv3 HV-CMOS sensor have been carried out using the Sentaurus Technology Computer Aided Design (TCAD) simulation software. Firstly, a comparison of a 2D model and a resource intensive 3D model was carried out, showing an agreement within 15% of the sensor properties, such as electric field, depletion depth and charge collection. However, there is a difference of 40% for the capacitance, indicating 3D simulations are better suited to capacitance measurements. The 2D model was then expanded to include a multi-pixel model for studies of charge sharing. Lab characterisations of planar sensor assemblies were undertaken to determine the quality of the bump-bonds and define regions with an acceptable level of working pixels for three assemblies. Calibrations were performed to convert the Time-over-Threshold (ToT) energy measurements and Digital-to-Analogue (DAC) threshold voltage steps into physical units. For the HV-CMOS assemblies, the analogue output of several pixels was compared to the ToT response of the CLICpix readout chip so that the simulation results could be converted to ToT and compared to the beam test data. The performance of the HV-CMOS assemblies was assessed at the CERN SPS using 120 GeV/c secondary beams. This was done over an incident angle range of 0-80° and showed excellent efficiency above 99.7% and a spatial resolution of 5-7 μm after eta-correction was applied to correct for non-linear charge sharing. The measurements were then compared to the simulations, showing a good agreement for the current-voltage, breakdown and charge collection properties. The validated simulations were used to investigate possible prospects for improved performance that can be applied in future sensor designs. Two avenues of investigation were explored: increasing the bulk resistivity and biasing from the backside. The largest improvement was for a back bias model with a resistivity of 1 kΩcm.