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This thesis shows that it is feasible to build modular FPGA systems which can dynamically change the hardware resources in the spatial and the temporal domains using existing tools and accelerators, to improve maintainability, adaptability, and accessibility for FPGA systems. To achieve this, first, a modular FPGA development flow is proposed to build an FPGA operating system, spanning both software and hardware level, where each component can be changed, reused, or ported to other systems with minor changes and recompilation steps. This modular flow removes the dependencies in existing infrastructures while supporting a wide range of FPGA use cases (static acceleration to dynamic multi-tenant acceleration) with easy-to-use software interfaces for both software and hardware developers. This platform is then extended using OpenCL to perform scheduling across two types of computing devices available on modern FPGA systems, i.e. both CPU and FPGA. To improve the adaptability of the system while maximising system utilisation, a novel concept called `resource elasticity' is proposed to allow the system to change the amount of resources used by a task transparently from the user in both space and time domain. Further, this is combined with the ability to dynamically move computation between CPU and FPGA (as well as collaborative execution) to allow changing the 1) device type (CPU or FPGA or both), 2) accelerator type, 3) number of compute units and 4) workload partitioning while supporting multi-tasking. Finally, this platform is used with multiple nodes to show how we can perform live migration across different FPGA nodes to allow system maintenance, load balancing and fault tolerance at the cluster level. Overall, with these contributions, this thesis enables building scalable FPGA systems that can support environments with dynamic workloads (e.g. cloud and edge computing) without compromising on the programmability, performance and ease of use for FPGAs. Further, the proposed solutions also improve the productivity for general FPGA users through a modular development flow and high-level user interfaces.

The storage hardware is evolving at a rapid pace to keep up with the exponential rise of data consumption. Recently, ultra-fast storage technologies such as nano-second scale byte- addressable Non-Volatile Memory (NVM), micro-second scale SSDs are being commercialized. However, the OS storage stack has not been evolving fast enough to keep up with these new ultra-fast storage hardware. Hence, the latency due user-kernel context switch caused by system calls and hardware interrupts is no longer negligible as presumed in the era of slower high latency hard disks. Further, the OS storage stack is not designed with multi-core scalability in mind; so with CPU core count continuously increasing, the OS storage stack particularly the Virtual Filesystem (VFS) and filesystem layer are increasingly becoming a scalability bottleneck. Applications bypass the kernel (kernel-bypass storage stack) completely to eliminate the storage stack from becoming a performance and scalability bottleneck. But this comes at the cost of programmability, isolation, safety, and reliability. Moreover, scalability bottlenecks in the filesystem can not be addressed by simply moving the filesystem to the userspace. Overall, while designing a kernel-bypass storage stack looks obvious and promising there are several critical challenges in the aspects of programmability, performance, scalability, safety, and reliability that needs to be addressed to bypass the traditional OS storage stack. This thesis proposes a series of kernel-bypass storage techniques designed particularly for fast memory-centric storage. First, this thesis proposes a scalable persistent transactional memory (PTM) programming model to address the programmability and multi-core scalability challenges. Next, this thesis proposes techniques to make the PTM memory safe and fault tolerant. Further, this thesis also proposes a kernel-bypass programming framework to port legacy DRAM-based in-memory database applications to run on persistent memory-centric storage. Finally, this thesis explores an application-driven approach to address the CPU side and storage side bottlenecks in the deep learning model training by proposing a kernel-bypass programming framework to move to compute closer to the storage. Overall, the techniques proposed in this thesis will be a strong foundation for the applications to adopt and exploit the emerging ultra-fast storage technologies without being bottlenecked by the traditional OS storage stack.

High-performance computing (HPC) is increasingly becoming more data-centric, involvinglarge data sets, rather than its historical focus on modeling and simulation. Sometimes, this data can be sensitive, provided by third parties to HPC centers or individual researchers, and raises security concerns regarding the confidentiality or integrity of the data. Our work aims to provide secure systems focused on HPC centers, without any significant performance reductions. Hardware-based trusted execution environments (TEEs) use hardware-backed techniques to provide some level of assurance for data and code confidentiality, and integrity. We first study the applicability of commercial hardware-based trusted execution environments (TEEs) to enable secure scientific computing. We rigorously analyze the performance impact of general purpose TEEs, AMD SEV, and Intel SGX, for diverse HPC benchmarks including traditional scientific computing, machine learning, graph analytics, and emerging scientific computing workloads. We also analyze the impact of the programming model required by these TEEs. The results show that commercial TEEs do not fit the HPC use case, either because their performance implications are intolerable, they require significant application changes (e.g., partitioning, linking applications against specific libraries), or their threat model does not include all system components that HPC applications might use. We provide a design point for enclaves that does not require an entire OS inside the enclave but can rely on a primarily untrusted OS for resource management. We implement a prototype data enclave, called DESC, with multithreading support on the RISC-V ISA that separates the management of the system from the protection of the sensitive data. We show how DESC allows an untrusted OS to maintain page tables, service system calls, and manage processes without compromising the enclave applications data confidentiality or integrity. Cycle-level architectural simulation of trusted execution environments (TEEs) can enable extensive design space exploration of these secure architectures. Existing architectural simulators that support TEEs are either based on hardware-level implementations or abstranalytic models. To this end, we enable a simulation environment using full-system architecture simulator, gem5, and a RISC-V based open source TEE, Keystone, and show how this simulation support opens new avenues for designing and studying these trusted architectures. Future HPC systems are expected to improve resource utilization by decoupling compute and memory extensively, leading to disaggregated architectures composed of different types of processing elements and remote memory pools. We also explore the expansion of our baseline TEE design (DESC) to provide scalable mechanisms that would allow a user to form a secure enclave spanning multiple processing elements.

In response to the growing number of cyber security attacks worldwide, layers of security remedies and patches have been introduced in recent hardware and software systems. Although these solutions have thwarted some attacks, the reactive approach of adding yet another layer of indirection is not a panacea for all security problems. The dissertation aims to create secure systems throughout the computing stack, mainly using two approaches: (1) mitigating security hazards in legacy systems, and (2) designing systems that provide isolation at the lowest possible layer.First, it highlights the security hazard of vulnerabilities in the graphics stack. To address this, two solutions are introduced. For desktops, it leverages GPU virtualization to provide web apps with a dedicated virtual graphics plane. For mobile devices, it designs a system to automatically repurpose the browser’s security checks to safeguard the mobile graphics interface.Second, it presents a hardware design that is composed of statically-partitioned and physically-isolated trust domains, namely the Split-Trust hardware design. It introduces a few simple, formally-verified hardware components to enable a program to gain provably exclusive and simultaneous access to both computation and I/O on a temporary basis. To manage this hardware, it presents OctopOS, an OS composed of mutually distrustful subsystems.

Hardware resource disaggregation is a solution that decomposes general-purpose monolithic servers into segregated, network-attached resource pools, each of which can be built, managed, and scaled independently. Despite its management, cost, and fault-tolerance benefits, hardware resource disaggregation is a drastic departure from the traditional computing paradigm and it calls for a top-down redesign on system software, hardware, and data center networks.This dissertation shows that it is possible to overcome the challenges of building and deploying hardware resource disaggregation solutions in real data centers, delivering its promises on better manageability, scalability, and cost.We first explored logical resource disaggregation for emerging persistent memory technologies. Logical resource disaggregation logically breaks the server boundary by building an indirection layer on top of monolithic servers to collectively expose a logical resource pool abstraction. However, we fail to overcome the inherent problems of monolithic servers. We then explored hardware resource disaggregation to overcome these limitations by physically separating hardware resources into network-attached pools. We emulated disaggregated devices using monolithic servers and built the first operating system designed for managing disaggregated resources. It provides backward compatible interfaces while delivering good performance. However, emulation incurs non-trivial overhead and has limited parallelism in serving highly-concurrent requests. To avoid such overhead, we then built the first publicly known hardware-based disaggregated memory device, which co-designs networking transport, virtual memory, and hardware. We soon realized that while an increasing amount of effort goes into disaggregating compute, memory, and storage, the network has been completely left out. The final piece of this dissertation proposes the concept of network disaggregation, which decouples network functionalities from endpoints and then consolidates them into a centralized network resource pool. We built a new hardware-based networking device along with a distributed runtime system to realize such a network resource pool. Together, these four pieces outline a practical path to enable hardware resource disaggregation solutions in real data centers, especially how one can navigate the complex trade-offs among performance, cost, and manageability.

Concurrency faults are one of the most damaging types of faults that can affect the dependability of today’s computer systems. Currently, concurrency faults such as process-level races, order violations, and atomicity violations represent the largest class of faults that has been reported to various Linux bug repositories. Clearly, existing approaches for testing such faults during software development processes are not adequate as these faults escape in-house testing efforts and are discovered during deployment and must be debugged. The main reason concurrency faults are hard to test is because the conditions that allow these to occur can be difficult to replicate, causing them to appear non- deterministically. Once these faults have been discovered during deployment and reported back to engineers, they are still very challenging to reproduce for the same reason. Furthermore, since concurrency faults can be complex, it is difficult for users to diagnose faults correctly. This can lead to bug reports that do not contain sufficient information or are totally incorrect. The goal of this dissertation is to make the process of reproducing concurrency faults more effective and efficient. Effectiveness means that we can reproduce faults more deterministically, and engineers can continue to debug applications in spite of incomplete reports. Efficiency means that using our proposed approaches, engineers take less time to perform the debugging process. This includes less time to develop detectors, less time to identify applications that can instigate reported faults, and less time to run the applications to reproduce reported faults. The results of our empirical evaluations reveal that the proposed systems collectively allow concurrency fault reproduction to be more effective, efficient, and accurate. Advisors: Witawas Srisa-an and Gregg Rothermel

Shared hardware resources in commodity multicore processors are subject to contention from co-running threads. The resultant interference can lead to highly-variable performance for individual applications. This is particularly problematic for real-time applications, which require predictable timing guarantees. It also leads to a pessimistic estimate of the Worst Case Execution Time (WCET) for every real-time application. More CPU time needs to be reserved, thus less applications can enter the system. As the average execution time is usually far less than the WCET, a significant amount of reserved CPU resource would be wasted. Previous works have attempted partitioning the shared resources, amongst either CPUs or processes, to improve performance isolation. However, they have not proven to be both efficient and effective. In this thesis, we propose several mechanisms and frameworks that manage the shared caches and memory buses on multicore platforms. Firstly, we introduce a multicore real-time scheduling framework with the foreground/background scheduling model. Combining real-time load balancing with background scheduling, CPU utilization is greatly improved. Besides, a memory bus management mechanism is implemented on top of the background scheduling, making sure bus contention is under control while utilizing unused CPU cycles. Also, cache partitioning is thoroughly studied in this thesis, with a cache-aware load balancing algorithm and a dynamic cache partitioning framework proposed. Lastly, we describe a system architecture to integrate the above solutions all together. It tackles one of the toughest problems in OS innovation, legacy support, by converting existing OSes into libraries in a virtualized environment. Thus, within a single multicore platform, we benefit from the fine-grained resource control of a real-time OS and the richness of functionality of a general-purpose OS.

Computer software is typically written in one language and then translated out of that language into the native binary languages of the machines the software will run on. Most operating systems, for instance, are written in the low-level language C and translated by a C compiler. Translation validation is the act of checking that this translation is correct. This dissertation presents an approach and framework for validating the translation of C programs, and three experiments which test the approach. Our validation approach consists of three components, a frontend, a backend and a core, which broadly mirrors the design of the C compiler. The three experiments in this dissertation exercise these three components. Each of these components produces a formal proof of refinement, and these refinement proofs compose to produce a proof that the binary is a refinement of the source semantics. This notion of refinement can then compose with correctness proofs for a C program, resulting in a verified binary. Throughout this work, our case study of interest will be the seL4 verified operating system kernel, compiled for the ARM instruction-set architecture, for which we will produce a verified efficient binary. The thesis of this work is that our translation validation approach offers us great flexibility. We can quickly produce verified binaries produced via many complex transformations without specifically addressing each such transformation. We can adapt our frontend to handle low-level source code which does not strictly respect the rules of the C language it is written in. We can also retarget our backend to address important timing concerns as well as correctness ones.

Modern computer hardware platforms are moving towards high core-count and heterogeneous Instruction Set Architecture (ISA) processors to achieve improved performance as single core performance has reached its performance limit. These trends put the current monolithic SMP operating system (OS) under scrutiny in terms of scalability and portability. Proper pairing of computing workloads with computing resources has become increasingly arduous with traditional software architecture. One of the most promising emerging operating system architectures is the Multi-kernel. Multi-kernels not only address scalability issues, but also inherently support heterogeneity. Furthermore, provide an easy way to properly map computing workloads to the correct type of processing resources in presence of heterogeneity. Multi-kernels do so by partitioning the resources and running independent kernel instances and co-operating amongst themselves to present a unified view of the system to the application. Popcorn is one the most prominent multi-kernels today, which is unique in the sense that it runs multiple Linux instances on different cores or group of cores, and provides a unified view of the system i.e., Single System Image (SSI). This thesis presents four contributions. First, it introduces a filesystem for Popcorn, which is a vital part to provide a SSI. Popcorn supports thread/process migration that requires migration of file descriptors which is not provided by traditional filesystems as well as popular distributed file systems, this work proposes a scalable messaging based file descriptor migration and consistency protocol for Popcorn. Second, multi-kernel OSs rely heavily on a fast low latency messaging layer to be scalable. Messaging is even more important in heterogeneous systems where different types of cores are on different islands with no shared memory. Thus, another contribution proposes a fast-low latency messaging layer to enable communication among heterogeneous processor islands for Heterogeneous Popcorn. With advances in networking technology, newest Ethernet technologies are able to support up to 40 Gbps bandwidth, but due to scalability issues in monolithic kernels, the number of connections served per second does not scale with this increase in speed.Therefore, the third and fourth contributions try to address this problem with Snap Bean, a virtual network device and Angel, an opportunistic load balancer for Popcorn's network system. With the messaging layer Popcorn gets over 30% performance benefit over OpenCL and Intel Offloading technique (LEO). And with NetPopcorn we achieve over 7 to 8 times better performance over vanilla Linux and 2 to 5 times over state-of-the-art Affinity Accept.

The difficulty of overcoming the disparity between processor speeds and data access speeds, a condition known as the von Neumann bottleneck, has been a source of consternation for computer hardware developers for many years.  Although a number of temporary solutions have been proposed and implemented in modern machines, these solutions have only managed to treat the major symptoms, rather than solve the root problem.  As the number of transistors on a chip roughly doubles every two years, the von Neumann bottleneck has continued to tighten in spite of these solutions, prompting some computer hardware professionals to advocate a paradigm shift away from the von Neumann architecture into something entirely new.  Many have begun advocating the relatively new technology of reconfigurable systems, popularly known as morphware.  The difficulty with adopting a new architectural paradigm, however, is that developers on both sides of the software-hardware spectrum must start from scratch, creating entirely new operating systems, hardware peripherals, application software, and user interfaces, all of which must seem familiar to the end user, yet still take advantage of the improvements morphware has to offer.  With this in mind, this thesis builds off of the fundamental theory and current implementations of morphware to describe the processes and products necessary to develop and deliver morphware to the average user as a viable alternative to current technology.

Managing energy consumption has become a critical issue for computer system designers. End-users are forced to charge battery-powered devices on a daily basis because battery technology has not kept pace with the demands of the power-hungry processors and peripherals used in today's mobile devices. Thousands of servers in data-centres also use power-hungry processors which result in huge costs for power and cooling. This is impacting our environment by accelerating global climate-change. To help mitigate these problems, processor manufacturers have implemented various power-management mechanisms, including dynamic voltage and frequency scaling (DVFS) and low-power idle modes, to reduce and manage the power consumption of their processors. These mechanisms are controlled by the operating system (OS) and in the past, their use could result in significant improvements in energy efficiency. However, changes in semiconductor technology are altering the effectiveness of these mechanisms. This thesis shows that on recent platforms, using DVFS results in only marginal reductions in system-level energy consumption for realistic workloads such as MPEG video playback. However, we find that the system-level energy consumption of lightly loaded web-servers can be reduced without impacting throughput or response latency. This results in an improvement in energy efficiency. However, several trends exist which are leading to diminishing returns from traditional power-management mechanisms. We analyse these trends to determine their impact on the effectiveness of the energy-management techniques used in systems today, and look into the future to see what might help to reduce the energy consumption of the computer systems of tomorrow.

The Plan 9 operating system from Bell Labs has broken a great deal of new ground in the realm of operating systems, providing a lightweight, network-centric OS with private namespaces and other important concepts. In Plan 9, all file operations, whether local or over the network, take place through the 9P file protocol. Although 9P is both simple and powerful, developments in computer and network hardware have over time outstripped the performance of 9P. Today, file operations, especially copying files over a network, are much slower with 9P than with protocols such as HTTP or FTP. 9P operates in terms of reads and writes with no buffering or caching; it is essentially a translation of the Unix file operations (open, read, write, close, etc.) into network messages. Given that the original Unix systems only dealt with files on local disks, it seemed that it may be necessary to extend 9P (and the file I/O programming libraries) to take into consideration the fact that many files now exist at the other end of network links. Other researchers have attempted to rectify the problem of network file performance through caching and other programmer-transparent fixes, but there is a second option. Streams (a continuous flow of data from server to client) allow programmers to read and write data sequentially (an extremely common case) while reducing the number of protocol messages and avoiding some of the problems with round-trip latency. By adding streaming to the 9P protocol and extending the regular POSIX I/O functions, this work allows programmers to perform sequential file operations at speeds much closer to those of HTTP. Files are transferred using out-of-band TCP connections between the client and server. In tests, streaming allowed files to be transferred at equal or superior speeds to HTTP.

Computer systems are experiencing great changes with rapid technology advancements in multi-core processors and rapid workload pattern shifts from computing-intensive to highly data-intensive applications. In today's multi-core computing environments, most resources on the memory hierarchies, e.g. space in the last level CPU caches, assesses to buffer pools, and throughput of disk storages, are shared and contended by a large number of threads concurrently running on multiple computing cores, and the performance of applications is more and more determined by how fast they can access their data. Compared with these rapid changes, operating systems as the resource managers have been evolved very slowly in several decades and have not been fully advanced to respond to these changes. The performance issues incurred by the increasingly complex structure and operations of these resources have not been effectively addressed at any level of computer systems. In this Ph.D. dissertation, we advance software systems to manage critical resources in increasingly complex computer architecture to respond the high demand of large-scale and data-intensive applications. Specifically, we will design and improve systems in the following focused areas. Firstly, at the multi-core processor level, we will make operating system be aware of the shared cache structure of multi-core processors to better utilize the processors by enhancing scheduling capability. We propose to develop new scheduling scheme to improve the effective caching capacity per core and/or per thread, and to minimize congestion in off-chip memory accesses by coordinating cache space sharing. Secondly, at the storage level, we will make operating system play an important role to improve disk accesses as fast as possible.We enable operating systems to effectively exploit "sequential locality" --- for the same amount of data, sequential accesses are several orders of magnitude faster than random accesses in disks. Finally, we improve the scalability of buffer pool management in software systems to service data accesses quickly from memory for as many concurrent threads as possible.

Operating System (OS) is the fundamental layer that provides and mediates accesses to a computer system’s resources for user application programs. The ever increasing size and complexity of the OS code bring the inevitable increase in the number of security vulnerabilities that can be exploited by attackers. A successful security attack on the OS has a profound impact because the OS runs at the highest processor privilege level. An OS kernel crash can freeze the entire system, terminate all running processes, and cause a long period of system unavailability. Given the increasing trend of OS security faults and the dire consequences of successful OS kernel attacks, we strive to make the OS kernel survivable, i.e. able to keep normal system operation despite security faults. This works makes several contributions. First, we propose an OS survivability scheme that consists of three inseparable components: (1) Security attack detection mechanism, (2) security fault isolation mechanism, and (3) recovery mechanism that resumes normal system operation. We analyze the underlying performance requirement for each of the components and propose simple but carefully-designed architecture support to reduce the performance overhead. When testing with real world security attacks, our survivability scheme automatically isolates the security faults from corrupting the kernel state or affecting other executing processes, recovers the kernel state and resumes execution. Second, in order to overcome the performance overhead incurred by the checkpointing- based recovery mechanism that extensively uses bulk memory copying and initialization operations, we propose efficient architecture support for improving bulk memory copying and initialization performance. While many of the current systems rely on a loop of loads and stores, or use a single copying instruction to perform memory copying, in this work we demonstrate that the key to significantly improving the performance is removing pipeline and cache bottlenecks of the code that follows the copying instructions. We show that the bottlenecks arise due to (1) the pipeline clogged by the copying instruction, (2) lengthened critical path due to dependent instructions stalling while waiting for the copying to complete, and (3) the inability to specify (separately) the cacheability of the source and destination regions. We propose FastBCI, an architecture support that achieves the granularity efficiency of a bulk copying/initialization instruction, but without its pipeline and cache bottlenecks. When applied to OS kernel buffer management, we show that on average FastBCI achieves anywhere between 23% to 32% speedup ratios, which is roughly 3×–4× of an alternative scheme, and 1.5×–2× of a highly optimistic DMA; When applied to our OS survivability scheme, we show that an average of 1.0% performance overhead can be achieved by our survivability scheme.

With the steady growth in Information Technology sector, managing complex infrastructure has proven to be a challenge for organizations, both big and small, in terms of maintaining a consistent environment across the board. In a product development industry, this consistency in the environment plays a key role in maintaining the overall productivity of the organization. Current Information Technology administrators have access to a wide array of open source and commercial tools for infrastructure management in terms of hardware as well as software configuration changes. As hardware support is provided by the appliance vendor, the complexity in managing the underlying operating system configuration changes poses a challenge. Although there is a wide array of open source tools available to achieve this objective, they may be far more complex than required, and may not be entirely portable within an existing environment. In many cases, the commercial solutions are not affordable depending on the size of the organization. This thesis investigates the currently available configuration management tools, and presents Linux operating system configuration management framework (LOSCMF) developed using open source tools and utilities. Linux operating system configuration management framework (LOSCMF) solution has been designed to perform complex operating system configuration changes by addressing the following three drawbacks found in the current configuration management solutions; usage of additional agents (system daemons), usage of complex configuration language, and usage of special scripting and programming languages. Each of the computer systems installed with the LOSCMF are grouped based on their current configuration level. A system administrator defines the necessary configuration changes that need to be applied either for a particular group or a logical combination of groups. These configuration changes are applied until a computer system confirms to a defined configuration state. The LOSCMF has both command line as well as web based reporting interfaces that can be used by the administrators to generate reports as per the requirement. The LOSCMF has been written using object oriented Perl, PHP and Bourne shell, and the underlying architecture is independent of the actual command or the scripting language, which would be performing the configuration change. The system administrators can choose to use any scripting or programming language of their choice to perform the configuration change. The LOSCMF solution can be used as a prototype within medium to large sized organizations for maintaining Linux operating system configuration changes. This thesis presents some of the benefits achieved using the LOSCMF approach such as a decrease in the administrative time, decrease in the support call volume, as well as a simple and effective mechanism for administrators to extract useful information on the fly.

Commodity operating systems are traditionally tuned to improve performance, but in the pursuit of faster operation, reliability is sacrificed. Therefore, common abstractions, such as asynchronous file system I/O, explicitly relax reliability guarantees (e.g., delay writes to disk by 30 seconds) in favor of better performance. The main concern of this thesis is to mitigate the performance/reliability tradeoff through the use of a general purpose mechanism, called Speculator, which implements multi-process speculative execution within the Linux kernel. Speculator is a tool for masking the latency of predictable, but slow, operations. It allows a critical, synchronous operation to be executed asynchronously. Thus, additional work is completed without sacrificing the benefits (i.e., the guarantees) of synchronous execution. Support for speculative execution is implemented using three techniques. First, Speculator tracks and propagates the causal dependencies (via speculations) of a process via inter-process communication mechanisms such as files, pipes, FIFOS and UNIX sockets. Second, Speculator buffers the output of speculative processes until the speculations upon which the output depends have been committed. Finally, should a speculation fail, Speculator can roll back each dependent kernel object and process. This dissertation shows that Speculator can be used to create new abstractions that replace synchronous abstractions within local file systems, distributed file systems and runtime security checks. Abstractions built using Speculator allow a pro grammer to develop applications for a reliable, synchronous abstraction while obtaining the performance of one that is asynchronous. Specifically, by using Speculator to build new abstractions, I can virtually eliminate the overhead of synchronous I/O for local file systems, build a distributed file system that provides strong consistency and safety guarantees while out-performing existing systems with weaker guarantees, and accelerate slow, sequential runtime security checks by parallelizing them across many cores. Finally, the speculative abstractions that I have built do not require application modification; the benefits of speculation are transparent.

Wang, Fei. Ph.D., Department of Computer Science and Engineering, Wright State University, 2006. A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration Reconfigurable machines can accelerate many applications by adapting to their needs through hardware reconfiguration. Partial reconfiguration allows the reconfiguration of a portion of a chip while the rest of the chip is busy working on tasks. Operating system models have been proposed for partially reconfigurable machines to handle the scheduling and placement of tasks. They are called OS4RC in this dissertation. The main goal of this research is to address some problems that come from the gap between OS4RC and existing chip architectures and the gap between OS4RC models and practical applications. Some existing OS4RC models are based on an impractical assumption that there is no data exchange channel between IP (Intellectual Property) circuits residing on a Field Programmable Gate Array (FPGA) chip and between an IP circuit and FPGA I/O pins. For models that do not have such an assumption, their inter-IP communication channels have severe drawbacks. Those channels do not work well with 2-D partial reconfiguration. They are not suitable for intensive data stream processing. And frequently they are very complicated to design and very expensive. To address these problems, a new chip architecture that can better support inter-IP and IP-I/O communication is proposed and a corresponding OS4RC kernel is then specified. The proposed FPGA architecture is based on an array of clusters of configurable logic blocks, with each cluster serving as a partial reconfiguration unit, and a mesh of segmented buses that provides inter-IP and IP-I/O communication channels. The proposed OS4RC kernel takes care of the scheduling, placement, and routing of circuits under the constraints of the proposed architecture. Features of the new architecture in turns reduce the kernel execution times and enable the runtime scheduling, placement and routing. The area cost and the configuration memory size of the new chip architecture are calculated and analyzed. And the efficiency of the OS4RC kernel is evaluated via simulation using three different task models.

Computers continue to get broken into, so intrusion analysis is a part of most system administrators' job description. System administrators must answer two main questions when analyzing intrusions: how did the attacker gain access to my system?, and what did the attacker do after they broke in?. Current tools for analyzing intrusions fall short because they have insufficient information to fully track the intrusion and because they cannot separate the actions of attackers from the actions of legitimate users. We designed and implemented a system for analyzing intrusions by using OS-level information flow to highlight the activities of an attacker. OS-level information flow is a collection of causal events which connect operating system objects. These causal events can be linked to form an information-flow graph which highlights the events and objects that are part of an attack. Information flow graphs can be used to help system administrators determine how an intruder broke into a system and what they did after the compromise. We developed BackTracker to determine how an intruder broke into a system. BackTracker starts with a suspicious object (e.g., malicious process, trojaned executable file) and follows the attack back in time, using causal events, to highlight the sequence of events and objects that lead to the suspicious state. Showing a graph of these causally-connected events and objects provides a system-wide view of the attack and significantly reduces the amount of data an administrator must examine in order to determine which application was originally exploited. We also developed ForwardTracker to determine the attacker's actions after the compromise. ForwardTracker starts from the application which was exploited and tracks causal events forward in time to display the information flow graph of events and objects that result from the intrusion. Furthermore, we designed and implemented Bi-directional Distributed BackTracker (BDB) which continues the backward and forward information flow graphs across the network to highlight the set of computers on a local network which are likely to have been compromised by the attacker.

This thesis presents the design and evaluation of an object-oriented (OO) operating system kernel for real-time embedded systems based on dataflow architecture. Dataflow is a software architecture that is well suited to applications that involve signal flows and value transformations. Typically, these systems comprise numerous processes with heavy inter-process communications. The dataflow style has been adopted for the control software for PEBB (Power Electronic Building Block) systems by the Center for Power Electronic Systems (CPES), Virginia Tech., which is involved in a research effort to modularize and standardize power electronic components. The goal of our research is to design and implement an efficient object-oriented kernel for the PEBB system and compare its performance vis-à-vis that of a non-OO kernel. It presents strategies for efficient OO design and a discussion of how OO performance issues can be ameliorated. We conclude the thesis with an evaluation of the advantages gained by using the OO paradigm both from the standpoint of the classically cited advantages of OO programming and other crucial aspects.

This thesis presents the design and evaluation of an operating system kernel specially designed for dataflow software. Dataflow is a style of software architecture that is well suited for control and "signal flow" applications. This architecture involves many small processes and lots of inter-process communication, which impose too much overhead on traditional RTOSes. This thesis describes design and implementation of the Dataflow Architecture Real-time Kernel (DARK). DARK is a reconfigurable, multithreaded and preemptive operating system kernel that introduces a special data-driven scheduling strategy for dataflow applications. It uses the underlying hardware for high-speed context switching between the kernel and applications, which is five times faster than the ordinary context switch. The features of the kernel can be configured according to performance requirements without change to the applications. Along with the performance evaluation of DARK, the performance comparison results of DARK with two commercial RTOSes: MicroC/OS-II and Analog Devices VDK++ are also provided.

Classes in C++ provide static encapsulation of objects, by generating code which contains specific knowledge about the internals of encapsulated objects. Static encapsulation occurs at compile time, and therefore cannot directly support the evolution of objects, since recompilation of source code is required if the internal layout changes. This also prohibits the use of distributed or persistent objects without first ensuring that the internal representations of the objects match the ones in the compiled code. Dynamic encapsulation occurs at run-time, and allows the compiled code to exist without the knowledge of any particular object representation. Abstract base classes with C++ virtual functions support a limited form of dynamic encapsulation, but only for objects originally designated to inherit from those classes. Some languages, such as Smalltalk, support dynamic encapsulation, but with significantly less performance than statically encapsulated languages. An object model using dynamic type-binding is presented which allows the flexibility of dynamic encapsulation with much of the efficiency of static encapsulation. With this model, objects can potentially communicate and migrate across address space and network boundaries without specific prior knowledge of representations, and can invoke functions on local objects with no more run-time overhead than standard C++ virtual function calls. This dynamic encapsulation model is incorporated into DC++, a C++-based language with extensions that allow for the dynamic encapsulation of existing C++ objects, and DECO (the Dynamic Encapsulator of C++ Objects), a utility for converting DC++ source code into C++.