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Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance.

Given how much of our current technology relies on the use of wireless sensors, improving communications technology directly benefits consumer products (smartphones, tablets, mobile devices of all kinds), healthcare (mobile monitoring devices, life-saving implants). Therefore, much higher communication speed, lower latency, and cheaper solutions are highly demanding as the technology is moving to the sixth generation (6G). The frequency band from 70 to 100 GHz and 125 to 160 GHz are currently the main focus band for the next generation of wireless communication. Different from wireless communication systems, optical communication involves the transfer of information using light rather than radio frequencies (RF). This method of data transportations has many advantages over standard telecommunications methods, such as improved bandwidth, speed, and power. Optical communication devices have applications in data connectivity (such as cloud storage), transportation networks, CATV systems, submarines, and defense technology. Indeed, as communication technology continues to advance, optical networking devices are becoming a much sought-after commodity. One of the most critical components in wireless communication and optical communication systems is the wideband power amplifiers (PA). Various semiconductor processes have been investigated to support the development of PA for 6G and optical communications systems. By far, Indium Phosphide (InP) and Silicon Germanium (SiGe) process have been proven to be great candidates for the development of the future system thanks to their superior performance in terms of cut-off frequencies. In addition, Indium Phosphide has a significantly higher output power and, therefore, is favorable for high power applications at high frequencies. However, as the operating frequencies emerge into the mm-W region, gain, linearity, and output power degrade rapidly, making the PA highly inefficient and unrealizable. In this dissertation, several original techniques are proposed and implemented to distributed amplifiers and wideband amplifiers. These techniques are applied to demonstrate high-performance power amplifiers up to 160 GHz, potentially enabling the future realization of 6G and the next generation of optical communications. The original techniques are listed as follows: 1. A new bandpass distributed amplifier (DA) using a wideband gain-boosting technique is introduced. A novel feedback network with a series inductor and a shunt capacitor is employed. The traditional theory has suggested that a series inductor only enhances narrowband gain, and a shunt capacitor decreases upper-frequency capacities. However, the combination of these components can obtain a wideband gain enhancement. The proposed amplifier achieves the record gain boosting over the wide bandwidth ever reported. 2. A wideband linearization technique for distributed amplifiers achieves the highest linearization bandwidth. The technique utilizes an auxiliary transistor that generates distortion components, which are the opposite sign of those generated by the main amplifier. The proposed prototype demonstrates the widest linearization bandwidth. 3. A 160 GHz DA with bandwidth improvement using 3-D interdigital capacitors and a 150 GHz using metal-insulator-metal (MIM) capacitors are designed in an InP process. This work demonstrates for the first time that 3-D interdigital capacitors can be used to improve input matching conditions and bandwidth of a distributed amplifier. 4. A linear wideband differential optical driver amplifier in a SiGe process for the next generation of optical communication systems is demonstrated. This is the first time a triple-stacked hetero junction bipolar transistor (HBT) with an emitter degeneration network is employed for optical drivers.

This work presents a fully-integrated double-quadrature Weaver receiver for monitoring the NIST time and frequency reference radio station WWV across multiple channels in the 2.5-20 MHz range. The design takes advantage of the Weaver architecture’s elimination of image rejection filters. The receiver uses a broadband low-noise amplifier (LNA) with an input-referred noise power spectral density (PSD) of 40 dB, noise figure (NF)

With the technical revolution on hardware and software of communication system, the fifth generation mobile communication systems (5G) is followed into the spotlight. In the 5G era, the frequency band will be in millimeter-wave region (24-60 GHz) and the available bandwidth can be the unthinkable in the 4G age. As a result, the data rate in the coming future can arrive >100 times higher than what we have currently employed. Its feature on high data rate and lowdelay will bring the significant improvement on the associated industries, such as autonomous vehicle, Internet-of-Tings (IoT)... However, the mm-wave signals also bring the more challenge on the 5G system design of the mobile and base station. It will suffer from the high atmospheric absorption in the communication, which is the dominant limitation on the long-distance communication in 5G. Therefore, it is essential to develop the 5G communication system and mm-wave ICs to overcome the physical limitation of mm-wave. The research projects in this dissertation, in consequence, focus on communication system design and mm-wave ICs for 5G. Also, it shows the advanced high data-rate ICs for IoT, which will be implemented of 5G era.

For the last decade, the size of complete 2.4GHz wireless modules containing everything but power have stagnated at ~1cm x 1cm. This is despite continued advances in semiconductor processes due to components needed by the core communication IC. Breaking this size barrier (which also sets a power and cost barrier) by eliminating all off-chip components is the goal of the Single-Chip Mote project, of which this dissertation is a part. The major components to be eliminated are antenna, battery, and crystal oscillator. Without these components, a complete wireless module could be the size of the RFIC silicon a few millimeters on a side, or less, instead of the size of the supporting PCB.Once those components are eliminated, advances in process scaling will lead to another size floor defined by the size of inductors, which do not scale with process. Inductor-based oscillators also put a floor on power consumption (dictated by desired swing versus achievable inductor quality factor) and, not being representable by digital cells, cannot be part of an integrated synthesis flow.In light of these limitations, understanding to what extent relaxation oscillators (the non-resonant oscillator family including RC oscillators and ring oscillators) can be used for communication is necessary to establish inductor-free performance limits and, more importantly, is necessary for future Single-Chip Mote scaling.Contrary to general opinion, FSK communication systems based on free-running RF ring oscillators do not exhibit catastrophically poor performance but are capable of good packet delivery rate (PDR 99% or better) with moderately higher tone spacing compared to typical low-power wireless specifications (~2x when communicating with COTS base station, ~6x when communicating to another ring-based radio). Methods to work around the high jitter of rings are established; this jitter is dominated by flicker noise and is poorly represented by simulators, making accurate simulation-based design difficult. Communication and complete sensor systems can be demonstrated, and system-level chip design at the core of this work can be taught to successive generations by adopting an industrial project-based approach.Updates and errata to this dissertation can be found at: http://people.eecs.berkeley.edu/~db/dissertation/

Modern and future communication and radar systems require highly reconfigurable RF front-ends to realize the vision of Software-Defined Radio (SDR), where a single digitally-enabled radio is able to cover multiple bands and multiple operating standards. However, in the increasingly hostile RF environment, filtering becomes a bottleneck for SDRs as the traditional off-chip filters are fixed frequency and bulky. Therefore, tunable filtering is a critical building block for the reconfigurable RF front-ends and on-chip implementations are needed to meet size and weight constraints. On-chip passive components are lossy, especially inductors, and to fulfill the tunability requirements a number of active circuit techniques, e.g. N-path, Q-enhanced, discrete-time filters etc., have been developed. Most of these active filtering techniques, however, are limited to RF frequency range of few GHz and below. Additionally, these techniques lack or have very limited bandwidth tunability. On the other hand, Q-enhanced tunable LC filtering has the potential to be implemented at Microwave frequencies from 4~20 GHz and beyond. In this dissertation, a number of Q-enhanced parallel synthesis techniques have been proposed and implemented to achieve high-order, frequency tunable, and wide bandwidth tunable filters. First, a tunable 4th-order BPF was proposed and implemented in Silicon Germanium (SiGe) BiCMOS technology. Along with center frequency tuning, the filter achieves first ever reported 3-dB bandwidth tuning from 2% to 25%, representing 120 MHz to 1.5 GHz of bandwidth at 6 GHz. A new set of design equations were developed for the 4th-order parallel synthesis of BPF. A practical switched varactor control scheme is proposed for large tuning ratio varactors to reduce the nonlinear contribution from the varactor substantially which improves the tunable LC BPF filter linearity. Second, parallel addition and subtraction techniques were proposed to realize tunable dual-band filters. The subtraction technique is implemented in SiGe BiCMOS technology at X and Ku bands with more than 50 dB of out-of-band attenuation. Finally, a true wideband band-reject filter technique was proposed for microwave frequencies using parallel synthesis of two band-pass filters and an all-pass path. The proposed band-reject scheme is tunable and wide 20 dB attenuation bandwidths on the order of 10s of MHz to 100s of MHz can be achieved using this scheme. The implementation of the proposed parallel synthesis techniques in silicon technology along with measured results demonstrate that Q-enhanced filtering is favorable at higher microwave frequencies. Therefore, such implementations are suitable for future wireless communication and radar systems particularly wide bandwidth systems on the order of 100s of MHz to GHz. Future research includes, high-order reconfigurable band-pass and band-reject filters, automatic tuning control, and exploring the parallel synthesis techniques in Gallium Nitride (GaN) technology for high RF power applications.

In the next few years, the 5th generation of mobile network employing the massive multiple input multiple output (MIMO), beam-forming, mm-wave frequency bands and carrier aggregation techniques will further increase the data rate to enrich the growing of mobile devices at the price of more complex multi-band, multi-frequency front end module (FEM). As an indispensable part of radio-frequency front end (RFFE), antenna switch circuit needs more restrict performance not only the basic insertion loss, isolation and power handling capability, but the requirements from higher data rate, low interference and better reliability of 5G application. To achieve those additional requirements for 5G RF switch with 45nm silicon-on-insulator (SOI) CMOS technology, this dissertation presents a novel multi-bands switch array structure to analysis the interference between switches in a single chip. The comprehensive study of switch array reveals that existing noise isolation techniques are insufficient and calls for novel in-die interference elimination. To reduce this in-die crosstalk, an above-silicon through back-end-of-line (BEOL) metal wall is developed as a practical solution with about 18.5dB (~98.6%) suppression. To reach a higher data rate with available frequency bands, millimeter wave (mm-wave) switches (28GHz/38GHz) has been demonstrated with the consideration of reliability issue of electrostatic discharge (ESD) which will introduce severe parasitic effects under this frequency level and degrade the performance of RFICs. The insertion loss and isolation together with ESD protection capability have been compared which shows the importance of ESD-RFIC co-design. Considering the necessity of accurate estimation for ESD performance, a novel methodology for both human body model (HBM) and charged device model (CDM) ESD protections using combined TCAD simulation and TLP/VFTLP measurements is depicted. To improve the accuracy of parasitic capacitance extraction, this dissertation introduces an enhanced de-embedded method with the help of HFSS simulation which reduces one third of the testchip size and gives a better reference for co-design.

The development of millimeter-wave phased arrays has been mostly based on silicon RFIC chips containing 8-16 channels and connected to antennas on organic printed circuit boards, or on wafer-scale phased arrays with on-chip antennas. Extending thewafer-scale array to a large number of elements results in an un-surmountable challenge, mainly that the phased-array chip may be much larger than a full reticle (approximately 22x22 mm2), and this is not allowed using standard integrated circuit design and layout rules. This dissertation focuses on the implementation of wafer-scale phased array with 64- and 256-elements using sub-reticle stitching techniques. An implementation of the largest single-chip wafer-scale phased-array ever built is demonstrated. The measured EIRP is 38 dBm and 45 dBm, with measured half-power beamwidth of 12.5 and 6 at 61 GHz for the 64- and 256-element phased arrays, respectively. This work allows the construction of large-scale (1000+ elements) phased-array systems, either on a single wafer or by assembling several of these chips together on a low cost board.

This dissertation focuses on the development of next generation wireless communications at millimeter-wave and sub-terahertz frequencies. As wireless providers experience a bandwidth shortage and cellular subscribers demand faster data rates and more reliable service, a push towards unused carriers fre- quencies such as 28 GHz, 60 GHz, and 180 GHz will alleviate network conges- tion while simultaneously providing massive bandwidths to consumers. This dissertation summarizes research in understanding millimeter-wave wireless propagation, the design and fabrication of millimeter-wave and sub-terahertz on-chip antenna arrays on an integrated circuit semiconductor process, and the accurate measurement of on-chip antenna radiation patterns in a wafer probe station environment.

This dissertation focuses on the development of next generation wireless communications at millimeter-wave and sub-terahertz frequencies. As wireless providers experience a bandwidth shortage and cellular subscribers demand faster data rates and more reliable service, a push towards unused carriers fre- quencies such as 28 GHz, 60 GHz, and 180 GHz will alleviate network conges- tion while simultaneously providing massive bandwidths to consumers. This dissertation summarizes research in understanding millimeter-wave wireless propagation, the design and fabrication of millimeter-wave and sub-terahertz on-chip antenna arrays on an integrated circuit semiconductor process, and the accurate measurement of on-chip antenna radiation patterns in a wafer probe station environment.

There has been a dramatic increase in wireless awareness among the user community in the past few years. As the wireless communication devices require more integration in terms of both hardware and software, the low-power integrated circuit (IC) solution has gained higher dedication and will dominate in the future radio-frequency IC (RFIC) design. Complementary Metal-Oxide Semiconductor (CMOS) process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. The transceiver is often the most power-hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator (VCO) which are essential building blocks of in the frequency synthesizer of the transmitter are among the major sources of power consumption. This work focuses on prescalers. The injection-locked frequency dividers (ILFD) were introduced in the recent past for low-power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However their range of operating frequency, also known as the locking range, is limited. ILFDs can be classified as LC tank, ring or relaxation oscillator based. There have been a lot of published works on the LC tank and ring oscillator based ILFDs. However, the one on relaxation oscillator based ILFD has been rarely reported, especially for RF applications. Besides, it is usually employed to implement a single division ratio such as 2, 3, 4 with an ILFD, while dual- or multi- moduli prescaler is more attractive to an RF synthesizer and are also rarely studied among published ILFDs. The goal of this work is to initially characterize the relaxation ILFD for RF applications. The locking range is optimized by the proposed topology. Besides, mathematical derivation is developed to verify the optimization. ILFD is also designed for different moduli with an easily controlled manner. Finally, the dual-modulus ILFD is also implemented based on the proposed structure. A prototype is fabricated in a 90-nm CMOS process and successfully tested.

Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and age. Driven by the desire to have a single piece of hardware that can provide multiple wireless services, attention has been directed to SDRs due to their programmable nature and the flexibility they can offer in operating over multiple standards. In addition, they can provide effective solutions to current challenges in wireless communication, such as spectrum overcrowding and inter-standard operability, as well as future challenges to come due to their upgradeability. Although SDRs have been around in the research community for over a decade, they have not reached the point of transitioning to the mass consumer market, size being one of the major obstacles. Numerous SDR hardware platforms have been developed demonstrating successful functionality, yet to this day most of them remain trapped in desktop/benchtop form factors which are not suited for mobility. A main factor contributing to the size of SDR units is the RF front end. Using current technology, wide-band operation of SDR RF front-ends is achieved by aggregating multiple dedicated components, each covering a portion of the frequency range. Recent technology advances have enabled the integration of wide frequency functionality inside a single integrated package. One example is a prototype RFIC transceiver chip from Motorola Research Labs which contains a complete direct conversion RF transceiver in a single chip, with a frequency coverage range of 100MHz-2.4GHz. RFIC5, the latest version of the chip, has additionally integrated high speed ADC and DAC units, leading to a significant reduction in the component count and the overall size of the SDR hardware. This thesis describes the implementation of a highly compact, SDR PC plug-in card, known as PicoRF. PicoRF is based on the Motorola's RFIC chip for the RF front-end functionality, while the combined computational power of a V5 FPGA and a PC host is used for waveform signal processing. An overlay gird consisting of an interconnection of PR slots is reserved on the FPGA to host the components of a signal processing pipeline which can be modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running on the PC host manages the overall system operation including the RFIC which is controlled through a custom developed API. The combination of the laptop host and the plug-in card form a small form factor, mobile SDR node that is one step towards satisfying both the performance and ergonomics demand of the consumer market.

The continual physical shrinking of semiconductor device dimensions is allowing for more integration between the previously segmented digital logic, memory, analog, and radio frequency domains – heralding the “More than Moore” era. Although able to meet the performance requirements for high-speed analog and RF, the devices are not guaranteed to always run at their typical sweet spot. The drifts from the optimal operation are due to many factors related to the silicon process and its response to changes in voltage and temperature, or what is collectively named PVT (Process, Voltage, Temperature) variations. These variations are a problem in all the integrated domains of the chip; however, RF circuits fail, in a more disproportionate manner, at sustaining proper operation over PVT. This makes them more prone to performance degradations and loss of yield when fabricated, in contrast to digital chips that can achieve near perfect yield. Putting both RF and digital together on a single chip, the hybrid system obviously inherits the lower yield, negating all the integration advantages. Therefore, the RF portions, in a sense, represent the SoC’s Achilles’ heel; in essence, an overly powerful and densely integrated chip can be made useless by a smaller underperforming portion of the chip.The ultimate goal is to increase the yield of the RF blocks by actively maintaining them in their optimal operating region. This proves to be a non-trivial task, as the operating conditions of the system at all times need to be known. For complex integrated systems, full verification during fabrication testing is quite prohibitive, in time and cost. A solution would be to build self-testing, and eventually self-healing, systems. Built-in-Self-Test (BiST) paradigms have already established themselves in the validation of digital blocks but are now becoming an increasingly active domain of research and development in RF. The notion of migrating RF test functionality to inside the chip brings us one step closer to cognitive-like radios. If RF blocks and systems can test for, and extract, their performance, then the ability to calibrate and cancel discrepancies can also be built into the system. Hence, Built-in-Self-Calibration (BiSC) can be layered on top of BiST to result in auto-correcting RF impairments at the block and system levels.In this dissertation, we discuss the problems set forth by increased integration and decreased circuit robustness. We also express the requirements for building efficient true self-test mechanisms using on-chip resources not only as value-added elements but also as necessary components for successful first-pass success of RF SoCs. An efficient RF sensor is presented along with the different possible built-in-tests for which it can be employed. The implementation of these on-chip test strategies aid in the development of calibration techniques that leverage the strengths of the more robust parts of the system to cover up the weaknesses of the others.

The past decade has witnessed rapid proliferation of wireless communications, which continues to enjoy a booming growth driven by unprecedented technology advances and strong consumer demands. New wireless technologies are being developed to provide people with high-speed low-cost multi-mode multi-task wireless communication environments with high quality of service (QoS). Of all the proposed wireless techniques, ultra wideband (UWB) is a promising technology, which becomes a front contender for various extremely high data throughput wireless applications, particularly for wireless video streaming and wireless sea-volume data transformation typically requiring a data speed up to several giga bit per second (Gbps).This dissertation describes research and integrated circuit (IC) implementation of a single-full-band carrier-free impulse-radio ultra wideband (IR-UWB) system. The IR-UWB transceiver adopts a simple-most-digital architecture with low design complexity, aiming to achieve the whole IR-UWB system-on-a-chip (SoC) in standard complementary metal-oxide-semiconductor (CMOS) process. Detail analysis for the IR-UWB system architecture is provided. Critical circuit building blocks, such as pulse generator (PG), BPSK modulation, receiver front-end low-noise amplifier (LNA) and correlator, are described both theoretically and experimentally. Adequate on-chip electrostatic discharge (ESD) protection is required for all IC chips and ESD protection design for radio-frequency (RF) IC emerges as a challenging design task as semiconductor IC technologies continue to advance into the very-deep-sub-micron (VDSM) regime. ESD protection for IR-UWB ICs is more challenging compared with narrow band IC designs. In this thesis, a novel ESD-RFIC co-design technique for UWB ICs was developed and experimentally verified. The interactions between ESD protection unit and core UWB IC were thoroughly investigated. The IR-UWB transmitter, front-end LNA and correlator ICs were designed with full ESD protection using the new ESD-RFIC co-design technique in this work.

Substrate noise coupling in integrated circuits is the process by which interference signals generated by high speed digital blocks cause parasitic currents to flow in the silicon substrate and couple devices in various parts of the circuits on this common substrate. In RFIC the switching noise couples to the sensitive analog circuits through the substrate causing degradation in performance and yield hit. Overcoming substrate coupling is a key issue in successful “system on chip” integration. In this thesis a substrate aware design flow is built, calibrated to silicon and used as part of the design flow to uncover substrate coupling problems in RFICs in the design phase. The flow is used to develop the first comprehensive RF substrate noise isolation design guide to be used by RF designers during the design phase. This will allow designers to optimize the design to maximize noise isolation and protect sensitive blocks from being degraded by substrate noise coupling. Several effects of substrate coupling on circuit performance will be identified and remedies will be given based on the design guide. Three case studies are designed to analyze the substrate coupling problem in RFICs. The case studies are designed to attack the problem from the device, circuit and system levels. On the device level a special emphasis is given to designing on chip inductors as an important device in RFIC. An accurate model is developed for a broadband fit of the inductor scattering parameters. This model is shown to be scalable and is proven to be accurate across various frequency bands and geometries. A special emphasis is put on the design for manufacturing effects that affect the design robustness. A circuit level case study is developed and results are compared to simulations and measurements to highlight the need for such a flow before tapping out to ensure a yielding part. The system level problem studied is a GSM receiver where the research results are directly applied to it as a demonstration vehicle to debug and resolve a system level substrate noise coupling problem that otherwise caused a product to be on the edge of malfunction.

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.

The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions. The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90 balance was achieved, over a specific range of LO power levels, with a square wave noise signal injected onto the mixer DC supply rails. The susceptibility of receiver I/Q balance to mixed-signal effects in a SoC environment motivates the second part of this dissertation --- the design of a phase and amplitude tunable, quadrature voltage-controlled oscillator (QVCO) for the on-chip synthesis of quadrature signals. The QVCO design, implemented in the Freescale (formerly Motorola) 0.18um SiGe:C RFBiCMOS process, uses two identical, differential LC-tank VCOs connected such that the two oscillator outputs lock in quadrature to the same frequency. The QVCO designs proposed in this work provide the additional feature of phase-tunability, i.e. the relative phase balance between the quadrature outputs can be adjusted dynamically, offering a simulated tuning range of ~90+/-10â ¹degree> in addition, a variable-gain buffer/amplifier circuit that provides amplitude tunability is introduced. One potential application of the QVCO is in a self-correcting RF receiver architecture, which, using the phase and amplitude tunability of the QVCO, could dynamically adjust the IF output quadrature phase and amplitude balance, in near real-time, in the analog-domain. The need for high-quality inductors in both the DCR and QVCO designs motivates the third aspect of this dissertation --- the characterization and modeling of on-chip spiral inductors with patterned ground shields, which are placed between the inductor coil and the underlying substrate in order to improve the inductor quality factor (Q). The shield prevents the coupling of energy away from the inductor spiral to the typically lossy Si substrate, while the patterning disrupts the flow of induced image currents within the shield. The experimental effort includes the fabrication and testing of a range of inductors with different values, and different types of patterned ground shields in different materials. Two-port measurements show a ~50% improvement in peak-Q and a ~20% degradation in self-resonant frequency for inductors with shields. From the measured results, a scalable lumped element model is developed for the rapid simulation of spiral inductors with and without patterned ground shields. The knowledge gained from this work can be combined and applied to a range of future RF/wireless SoC applications. The designs developed in this dissertation can be ported to other technologies (e.g. RF CMOS) and scaled to other frequency ranges (e.g. 24GHz ISM band) to provide solutions for emerging applications that require low-cost, low-power RF/microwave circuit implementations.

Over the last few decades, the susceptibility of integrated circuits to electrostatic discharge (ESD) induced damages has justified the use of dedicated on-chip protection circuits. Design of robust protection circuits remains a challenging task because ESD failure mechanisms have become more acute as device dimensions continue to shrink. A lack of understanding of the ESD phenomena coupled with the increased sensitivity of smaller devices and time-to-market demands has led to a trial-and-error approach to ESD-protected circuit design. Improved analysis capabilities and a systematic design approach are essential to accomplish the challenging task of providing adequate protection to core circuit(s). The design of ESD protection circuitry for RFIC's has been relatively slow to evolve, compared to their digital counterparts, and is now emerging as a new design challenge in RF and high-speed mixed-signal IC development. Sub-circuits which are not embedded in a single System-on-Chip (SOC), such as RF Power amplifiers (PAs), are of particular concern as they are more susceptible to the various ESD events. This thesis presents the development of integrated ESD protection circuitry for two RFIC Power Amplifier designs. A prototype PA for 2.4 GHz Wireless Local Area Network (WLAN) applications was redesigned to provide protection to the RF input and the PA Control pins. A relatively new technique known as the L-C tank approach was used to protect the RFinput while a standard diode ring approach was used to protect the control line. The protection techniques studied were subsequently extended to a completely protected three-stage PA targeting 1.9 GHz Digitally Enhanced Cordless Telephone (DECT) applications. An on-chip shunt-L-series-C input matching network was used to provide ESD protection to the input pin of the DECT PA. A much more area efficient (as compared to the diode ring technique) Zener diode approach was used to protect the control and signal lines. The PA's RF performance was virtually unaffected by the addition of the protection circuits. Both PAs were designed in a commercially available 0.5 ìm SiGe-HBT process. The partially protected WLAN PA was fabricated and packaged in a 3mm x 3mm Fine Pitch Quad Flat Package FQFP-N 12 Lead package and had a measured ESD protection rating of ± 1kV standard Human Body Model (HBM) ESD test. The simulated DECT PA demonstrated +1.5kV/-4kV HBM performance.

Automotive radar systems at 77 GHz are built using expensive III-V semiconductor such as GaAs or InP, and this makes the price of the adaptive cruise control (ACC) system too high for most cars. The emerging SiGe and RF MEMS technologies are used in this thesis to implement low cost and high performance mm-wave components, thereby opening the venue for use in virtually all automotive platforms. State-of-the-art W-band 3-bit phase shifters using distributed MEMS transmission lines on glass substrates were developed. A figure of merit of 93--100°/dB was achieved at 75--110 GHz and the measured results fit very well with the full-wave simulations for a single-cell combined with ADS network analysis for the entire phase shifter. Careful loss analysis indicates that the performance can be improved to 150--200°/dB if integrated on quartz substrates. High-efficiency monolithic Ku- and Ka-band balanced frequency doublers were built using commercial SiGe bipolar process (Atmel Corporation, SiGe2-RF). The Ku-band design presents an output power of 5--6 dBm from 15.4--18 GHz and the corresponding power added efficiency (PAE) is 9.2%. The Ka-band design demonstrates an output power of 10.5 dBm at 36 GHz with a PAE of 6.4% and a high spectral purity with a fundamental suppression of 35 dB. To our knowledge, these are the best results for active doublers using any technology. A novel SiGe 77 GHz subharmonic balanced mixer is presented with a goal to push the technology to its limit (SiGe2-RF transistor f T = 80 GHz). This new topology uses a compact input network to not only achieve the isolation between LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate the conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P1db of -8 dBm. The circuit demonstrates that SiGe subharmonic mixers have comparable performance with GaAs designs, at a fraction of the cost.

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered.

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit.

The dramatic increase in market demand for wireless products has inspired a trend for new designs. These designs are smaller, less expensive, and consume less power. A natural result of this trend has been the push for components that are more highly integrated and take up less real estate on the printed circuit board (PCB). Major efforts are underway to reduce the number of integrated circuits (ICs) in newer designs by incorporating several functions into a single chip. Availability of newer technologies such as silicon bipolar with complementary metal oxide semiconductor (BiCMOS) has helped facilitate this move toward more complex circuit topologies onto one die. BiCMOS achieves efficient chip area utilization by combining bipolar transistors, suited for higher frequency analog circuits with CMOS transistors that are useful for digital functions and lower frequency analog circuits. A voltage controlled oscillator (VCO) is just one radio frequency (RF) circuit block that can benefit from a more complex semiconductor process like BiCMOS. This thesis presents the design and evaluation of an integrated VCO in the IBM 5S BiCMOS process. IBM 5S is a 0.5 um, single poly, five-metal process with surface channel PFETs and NFETs. The process also features self-aligned extrinsic base NPN bipolar devices exhibiting ft of up to 24 GHz. The objective of this work is to obtain a VCO design that provides a high degree of functionality while maximizing performance over environmental conditions. It is shown that an external feedback and resonator network as well as a bandgap voltage referenced bias circuit help to achieve these goals. An additional objective for this work is to highlight several pragmatic issues associated with designing an integrated VCO capable of high volume production. The Clapp variant of the Colpitts topology is selected for this application for reasons of robust operation, frequency stability, and ease of implementing in integrated form. Design is performed at 560 MHz using the negative resistance concept. Simulation results from Pspice and the Agilent ADS are presented. Implementation related issues such as bondwire inductances and layout details are covered. The VCO characterization is shown over several environmental conditions. The final nominal design is capable of: tuning over 150 MHz (22%) and delivering â 4.2 dBm into a 50 Ohm load while consuming only 9mA from a 3.0V supply. The phase noise at these conditions is -92.5 dBc/Hz at a frequency offset of 10 kHz from the carrier. Finally, the conclusion of this work lists some suggestions for potential future research.

The demand for efficient, lightweight consumer products created the need for miniaturization of passive components especially inductors which are some of the bulkiest parts of an integrated system. The purpose of the work described here was to study toroidal inductor structures since they were compact and self-shielding. Toroidal inductors were modeled using a commercial electromagnetic simulator. The results show that these structures have good characteristics in terms of inductance, quality factor and area. Three different structures are fabricated and experimentally characterized using the HP Vector Network Analyzer. We also make several observations about the effect of the placement of each pair of top and bottom metal strips with respect to each other on the flux linkage and hence, the inductance and quality factor of the inductor.

Over the past decade there has been an explosion in the demand for wireless mobile personal communications systems (PCS), a trend that shows no signs of slowing down in the foreseeable future. This demand has created a greater need for low-cost, low-power, compact system solutions. As a result, "single-chip" implementations of wireless functions have received a significant amount of attention. A significant roadblock to complete integration of these functions is the requirement for high-Q resonators in RF filter and tank circuits. Current on-chip techniques being used to realize monolithic RF resonators based on planar inductors, capacitors and active circuits are accompanied by problems such as high loss, large chip area and high power consumption. An alternative to these on-chip solutions is the use of monolithically integrated electromechanical devices. This thesis describes the modeling, fabrication and characterization of nanoelectromechanical (NEM) single crystal silicon resonators. The potential advantages associated with these devices are high-Q, small die area and low power consumption. The development of such devices compatible with modern integrated circuit fabrication techniques offers the possibility for integration of high performance RF filters and resonators onto a single RFIC chip. The advantageous characteristics of these resonators could lead to mobile PCS devices with lower cost and increased battery life. The NEM resonator designs investigated in this work are fabricated using an electron-beam lithography based surface machining process in silicon-on-insulator technology. Various design, fabrication and testing issues are discussed. The feasibility of lateral capacitive actuation and detection in such structures is examined.

This thesis presents a novel Subharmonic Double Balanced Mixer topology suitable for implementation in Radio Frequency Integrated Circuit (RFIC) technologies including Silicon Bipolar, BiCMOS, HBT and CMOS process technologies. A 1.9 GHz design fabricated in a 0.35mu BiCMOS process is presented and verified with testing on the fabricated die. Qualitative and quantitative analyses are presented to describe the operation and performance of this new mixer topology. Finally, simulation results for a more linear version of the Subharmonic Double Balanced Mixer topology are presented.

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed.

The rapid development of wireless applications has created a demand for low-cost, compact, low-power hardware solutions. This demand has driven efforts to realize fully integrated, "single-chip" systems. While substantial progress had been made in the integration of many RF and baseband processing elements through the development of new technologies and refinements of existing technologies, progress in the area of fully monolithic filters has been limited due to the losses (low Qs) associated with integrated passive elements in standard IC processes. The work in this thesis focuses on the development low-loss, Q-enhanced LC filters in GaAs E/D-SAGFET technology. This thesis presents a methodology for designing Q-enhanced LC resonators and low-loss, monolithic LC filters based on these resonators. The first phase of this work focused on the Q-enhancement of LC resonator structures using FET-based active negative resistance circuits. Three passive resonators were designed, fabricated, and measured to determine their loss and frequency response. Furthermore, six Q-enhanced resonators were designed, fabricated, and measured to compare the performance of various negative resistance circuit designs. In the second phase of this work, four of these Q-enhanced resonator designs were used to implement fully-integrated second-order Butterworth bandpass filters. Each filter was designed for a 60 MHz, -3 dB bandwidth centered at 1.88 GHz, corresponding to the North American PCS transmit band. The best filter design achieves 0 dB of passband insertion loss while consuming 16 mA of current from a 3 V source (48 mW). Passband gain (up to 15 dB) can be achieved with increased bias current before instability is encountered. The filter provides more than 30 dB of rejection at 1.7 and 2 GHz and more than 70 dB of rejection below 1.5 GHz. In the filter passband, the noise figure is 12 dB and the output 1 dB compression point is -18 dBm. These Q-enhanced LC filters have potential application as image-reject filters in GaAs integrated transceiver designs.

In 1997 the Federal Communications Commission (FCC) released 300 MHz of spectrum between 5-6 GHz designated the unlicensed national information infrastructure (U-NII) band. The intention of the FCC was to provide an unlicensed band of frequencies that would enable high-speed wireless local area networks (WLANs) and facilitate wireless access to the national information infrastructure with a minimum interference to other devices. Currently, there is a lack of cost-effective technologies for developing U-NII band components. With the commercial market placing emphasis on low cost, low power, and highly integrated implementations of RF circuitry, alternatives to the large and expensive distributed element components historically used at these frequencies are needed. Silicon Germanium (SiGe) BiCMOS technology represents one possible solution to this problem. The SiGe BiCMOS process has the potential for low cost since it leverages mature Si process technologies and can use existing Si fabrication infrastructure. In addition, SiGe BiCMOS processes offer excellent high frequency performance through the use of SiGe heterojunction bipolar transistors (HBTs), while coexisting Si CMOS offers compatibility with digital circuitry for high level 'system-on-a-chip' integration. The work presented in this thesis focuses on the development of a SiGe RFIC front-end for operation in the U-NII bands. Specifically, three variants of a packaged low noise amplifier (LNA) and a packaged active x2 sub-harmonic mixer (SHM) have been designed, simulated and measured. The fabrication of the Rifts was through the IBM SiGe foundry; the packaging was performed by RF Micro devices. The mixer and LNA designs were fabricated on separate die, packaged individually, and on-chip matched to a 50 ohm system so they could be fully characterized. Measurements were facilitated in a coaxial system using standard FR4 printed circuit boards. The LNA designs use a single stage, cascoded topology. The input ports are impedance matched using inductive emitter degeneration through bondwires to ground. One version of the LNA uses an shunt inductor/series capacitor output match while the other two variation use a series inductor output match. Gain, isolation, match, linearity and noise figure (NF) were used to characterize the performance of the LNAs in the 5 - 6 GHz frequency band. The best LNA design has a maximum gain of 9 dB, an input VSWR between 1.6:1 and 2:1, an output match between 1.7:1 and 3.6:1, a NF better than 3.9 dB and an input intercept point (IIP3) greater than 5.4 dBm. The LNA operates from a 3.3 V supply voltage and consumes 4 mA of current. The SHM is an active, double-balance mixer that achieves x2 sub-harmonic mixing through two quadrature (I/Q) driven, stacked Gilbert-cell switching stages. Single-ended-to-differential conversion, buffering and I/Q phase separation of the LO signal are integrated on-chip. Measurements were performed to find the optimal operating range for the mixer, and the mixer was characterized under these sets of conditions. It was found that the optimal performance of the mixer occurs at an IF of 250-450 MHz and an LO power of -5 dBm. Under these conditions, the mixer has a measured conversion gain of 9.3 dB, a P_1-dB of -15.7 dBm and an 2LO/RF isolation greater than 35 dB at 5.25 GHz. At 5.775 GHz, the conversion gain is 7.7 dB, the P1-dB is -15.0 dBm, and the isolation is greater than 35 dB. The mixer core consumes 9.5 mA from a 5.0 V supply voltage. This work is sponsored by RF Microdevices (RFMD)through the CWT affiliate program.The author was supported under a Bradley Foundation fellowship.

Networked wireless sensor systems have the potential to play a major role in critical applications including: environmental monitoring of chemical/biological attacks; condition-based maintenance of vehicles, ships and aircraft; real-time monitoring of civil infrastructure including roads, bridges etc.; security and surveillance for homeland defense systems; and battlefield surveillance and monitoring. Such wireless sensor networks can provide remote monitoring and control of operations of large-scale systems using low-power, low-cost, "throw-away" sensor nodes. This thesis focuses on two aspects of wireless sensor node development: (1) post-IC assembly of nanosensor devices onto prefabricated complementary-metal-oxide-semiconductor (CMOS) integrated circuits using a technique called dielectrophoretic (DEP) assembly; and (2) design of a low-power SiGe BiCMOS multi-band ultra-wideband (UWB) transmitter for wireless communications with other nodes and/or a central control unit in a wireless sensor network. For the first part of this work, a DEP assembly test chip was designed and fabricated using the five-metal core CMOS platform technology of Motorola's HiP6W low-voltage 0.18_m Si/SiGe BiCMOS process. The CMOS chip size was 2.5mm x 2.5 mm. The required AC signal for assembling nanowires is provided to the bottom electrodes defined in the Metal 4 (M4) layer of the IC process. This signal is then capacitively coupled to the top/assembly electrodes defined in the top metal (M5) layer that is also interconnected to appropriate readout circuitry. The placement and alignment of the nanowires on the top electrodes are defined by dielectrophoretic forces that act on the nanowires. For proof of concept purposes, metallic rhodium nanowires ((length = 5μm and diameter = 250 nm) were used in this thesis to demonstrate assembly onto the prefabricated CMOS chip. The rhodium nanowires were manufactured using a nanotemplated electroplating technique. In general, the DEP assembly technique can be used to manipulate a wider range of nanoscale devices (nanowire sensors, nanotubes, etc.), allowing their individual assembly onto prefabricated CMOS chips and can be extended to integrate diverse functionalized nanosensors with sensor readout, data conversion and data communication functionalities in a single-chip environment. In addition, this technique provides a highly-manufacturable platform for the development of multifunctional wireless sensor nodes based on assembled nano-sensor devices. The resistances of the assembled nanowires were measured to be on the order of 110 Ω consistent with prior prototype results. Several issues involved in achieving successful assembly of nanowires and good electrical continuity between the nanowires and metal layers of IC processes are addressed in this thesis. The importance of chemical/mechanical planarization (CMP) technique in modern IC processes and considerations for electrical isolation of readout circuit from the assembly sites are discussed. For the second part of this work, a multi-band hopping ultrawideband transmitter was designed to operate in three different frequency bands namely, 4.8 GHz, 6.4 GHz and 8.0 GHz. As a part of this effort, this thesis includes the design of a CMOS phase/frequency detector (PFD), a CMOS pseudo-random code generator and an on-chip passive loop filter, which were designed for the multi-band PLL frequency synthesizer. The CMOS PFD provided phase tracking over a range of -2π to +2π radians. The on-chip passive loop filter was designed for a 62_ phase margin, 250 μA-charge pump output current and 4 MHz-PLL loop-bandwidth. The CMOS pseudorandom code generator provided a two-bit output that helped switch the frequency bands of the UWB transmitter. With all these components, along with a BiCMOS VCO, a CMOS charge pump and a CMOS frequency divider, the simulated PLL frequency synthesizer locked within a relatively short time of 700ns in all three design frequency bands. The die area for the multi-band UWB transmitter as laid out was 1.5 mm x 1.0 mm. Future work proposed by this thesis includes sequential assembly of diverse functionalized gas/chemical nanosensor elements into arrays in order to realize highly sensitive "electronic noses". With integration of such diverse functionalized nano-scale sensors with low-power read-out and data communication system, a versatile and commercially viable low-power wireless sensor system can be realized.

The recent trend in the RF and microwave industry has been a move towards increasing the number of components realized on one radio frequency integrated circuit (RFIC) (or microwave integrated circuit (MIC)). This trend has resulted in complex RFICs which often require reactive as well as other circuit components to be supplied in the form of an external circuit. Because the manufacturer's suggested circuit is often developed with a specific application in mind, the same circuit may not satisfy the demands of another application. Provided the necessary functionality and connections are possible, the external circuit may be altered such that the requirements of the other application can be met, thus extending the flexibility of the RFIC. The work presented here is focused on investigating modifications to RF Microdevices' suggested external circuit for the RF29X5 family of low cost, half duplex, FM/AM/ASK/FSK RFIC transceivers originally intended for operation in the 433, 868, or 902-928 MHz industrial, scientific, and measurement (ISM) bands. Examinations of the operating principles of the transceiver components were performed which facilitated the identification of suitable modifications. Among the modifications identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in a potentially improved implementation of the VCO by modifying the internal active circuitry as well.